Addressing Modes

The ARMv8 has simple addressing modes based on load and store principles. ARM cores perform Arithmetic Logic Unit (ALU) operations only on registers. The only supported memory operations are the load (which reads data from memory into registers) or store (which writes data from registers to memory). By use of LDR/STR instructions and their available options, all the data must be loaded in the general-purpose registers before the operations on them can be performed. Multiple addressing modes can be used for load and store instructions:

The register is used to store the address of the data in the memory. Or the data will be stored in the memory at the address given in the register.

LDR X0, [X1] @ fill the register X0 with the data located at address stored in X1 register

STR X1, [X2] @ store the content for register X1 into the memory at location given in the X2 register

An offset to the base register is added before the memory access. The address is calculated by adding the two registers: [X1, X2] will result in X1+X2. The register X1 represents the base register, and X2 represents the offset. The offset value can also be negative, but the final, calculated address must be positive.

LDR X0, [X1, X2] @ address pointed to by X1 + X2

STR X2, [X4, X3] @ address pointed to by X4 + X3

The LDR instruction machine code also allows a shift operation to the offset register while maintaining the same addressing mode.

LDR X0, [X1, X2, LSL #2] @ address is X1 + (X2*4)

The ARM separates this addressing mode because the register that points to the address in memory can now be modified. The value will be added to the register before the access is performed.

LDR X0, [X1, #32]! @ read the data into X0 register from address pointed to by X1+32, then X1=X1 + 32

The exclamation mark at the end of the closing bracket indicates that the value of the register X1 must be increased by 32. After that, the memory access can be performed.

Like with the previous addressing mode, this one is also separated. As the addressing mode says, ‘post’ means that the value of the register will be increased after performing the memory access.

LDR X0, [X1], #32 @ read X0 from address pointed to by X1, then X1=X1 + 32

There are some other addressing modes available. Some addressing modes are used only for function or procedure calls, while others combine previously described addressing modes. This subsection will introduce some of the other available addressing modes.

• Register to register, also called register direct addressing mode. It is used to copy data from one register to another. No memory access is performed with such operations.
• Literal addressing, alternatively, the immediate addressing mode is used to identify the data directly in the instruction.
• PC-relative addressing

Literal addressing mode allows the use of literal addresses in the program code. Something similar is done with function names, but in this situation, the data are addressed by literal names. PC-relative addressing Some instructions allow loading (and storing) a pair of data (LDP and STP instructions).

LDP X0, X1, [X2, #32] @ read X0 from address pointed to by X2, and then read X1 from X2 + 32

These instructions will be used to call a function or procedure.

The load and store instructions also work with 32-bit registers. Load instructions include additional options that can be used not only for data loading but also for other operations on the data in the register. For example, to load a single data byte into the register, use the LDRB instruction. If a byte holds a negative value, the entire register must preserve the sign – this is called sign extension and is performed with the LDRSB instruction. Like, for example, the value -100 in hexadecimal is 0x9C (in binary 2’s complement 10011100).

The data are loaded from memory, and the sign bit is preserved only for a 32-bit wide value when the destination register is addressed as a 32-bit register. If the 64-bit register is used as the destination, the sign bit is preserved in the entire 64-bit register.

Zero extension is only available for 32-bit registers because the most significant bytes are cleared when a 32-bit register is written.

This is not a real addressing mode, but some instructions allow the addressing to be a bit more complex. Loading from memory (or storing in it) data into the vector register. the LD1, LD2, LD3 and LD4 instructions loads vector register:

LD1 {V1.16b}, [X1] @ Load 16 bytes (128 bits) from memory address X1 into the vector register V1.

LD1 {V0.4s, V1.4s}, [X1], #32 @ Load first 16 bytes in the V0 register and next 16 bytes into the V1 register (32 bytes in total). X1 is incremented by 32 after the load.

LD1 {V0.4s}, [X1, X2, LSL #4], #32 @ Load 16 bytes into V0 register with register offset: the efective address used to load the data is = x1 + (X2 «4)

Unprivileged addressing mode

The unprivileged addressing mode simulates EL0 memory access even when the CPU is running at EL1 exception level. Such an addressing mode is used to copy the data between different exception levels.

LDTR W0, [X1]

STTR W2, [X1]

These two instruction examples load/store a 32-bit word from/to memory at address X1, but the data access is performed using EL0 permissions even if the CPU is currently running in EL1. If X1 register points to invalid user memory, the load instruction will fail with a fault.

Atomic/exclusive addressing

Exclusive addressing mode allows the processor to update shared memory between processes without data races. Exclusive operations use a load–reserve/store–conditional technique. Instruction LDXR reads a value from memory and marks the address so the core can detect interference from other processes that may also read the exact memory location. A matching STXR only commits the new value if no conflicting write has occurred. If another process (or core) has changed the location in the meantime, the store fails.

LDXR X0, [X1] @ Load 64-bit value from memory address pointed by X1 and mark the address in the CPU exclusive monitor.

Such instructions can be used as part of an atomic read-modify-write operation.

STXR X0, X1, [X2] @ Try to store X1 into memory at [X2] address. If no other process or CPU writes to this address since the LDXR instruction, the register X0 = 0 and the store succeeds. Otherwise the store has failed and X0 = 1

Complete example of atomic read-modify-write technique:

rmw:
LDXR X0, [X1] @ load the current value and set exclusive monitor
ADD X0, X0, #1 @ compute new value
STXR W2, X0, [X1] @ try to store the new value atomically
CBNZ W2, rmw @ if store failed, retry

Atomic read-modify-write instructions such as LDADD, CAS, and SWP perform the entire update in a single step. All these operations use a simple [Xn] addressing form to keep behaviour predictable. This model supports locks, counters, and other shared data structures without relying on heavier synchronisation mechanisms.

LDADD W0, W1, [X2] @ atomically load the data, modify the value and write back to the memory.
Analogically, this instruction can be described with pseudocode:

oldValue = [X2]
[X2] = oldValue + W0
W1 = oldValue

Another example of the CAS instruction: atomic compare-and-swap.

CAS X0, X1, [X2] @ atomically compare the value of [X2] with X0. If [X2]==X0 then [X2]=X1, otherwise tha data in the memory are left unchanged

Similarly, the CAS instruction performs a data swap.

SWP X3, X4, [X5]
oldValue = [X5]
[X5] = X4
X3 = oldValue

Atomic addressing mode does not have immediate offset, register offset, or pre-indexing/post-indexing options. Basically, the atomic addressing uses simple memory addressing.