ESP32-H2 is family of microcontrolers (SoC) that combines IEEE 802.15.4 connectivity with Bluetooth 5 (LE). The system does not have a Wi-Fi protocol but Thread and Zigbee protocols are available. ESP32-H2 has been certified as a “Zigbee-Compliant Platform” and has officially become a “Thread-Certified 1.3.0 Component”. The SoC is powered by a single-core, 32-bit RISC-V microcontroller that can be clocked up to 96 MHz. The ESP32-H2 has been designed especially for connected devices with low power consumption and security in mind. ESP32-H2 has 320 KB of SRAM with 16 KB of Cache, 128 KB of ROM, 4 KB LP of memory, and a built-in 2 MB or 4 MB SiP flash. It has 19 programmable GPIOs with support for ADC, SPI, UART, I2C, I2S, RMT, GDMA and LED PWM. For now the ESP32-H2 family documentation is available as preliminary information only.

(Figure ##REF:esp32h2_functions##) shows functional block diagram of ESP32-H2 chip. Main common features of the ESP32-H2 are ^[1]:

Processors

• Main processor: 32-bit RISC-V single-core CPU up to 96MHz,
  • Cores: 1

Wireless connectivity

• Bluetooth: v5.0 Bluetooth Low Energy (BLE) ( speed: 125 Kbps - 2 Mbps)
• 802.15.4-2015: up to 250 kbps; stacks includes Thread 1.3 , Zigbee 3.0 , Matter, HomeKit, MQTT

Memory: Internal memory

• Embedded flash 2 or 4 MiB
• ROM: 128 KiB (for booting and core functions).
• SRAM: 320 KiB (for data and instructions).
• LP memory: 4 KB of SRAM that can be accessed by the CPU. It can retain data in Deep-sleep mode
• eFuse - 4 Kbit: 1792 bits are reserved for user data, such as encryption key and device ID

Peripheral Input/Output

• 19 x GPIO
• 2 x 12-bit ADCs (analog-to-digital converter) up to 5 channels,
• Internal temperature sensor.
• 3 × SPI (Serial Peripheral Interface),
• 2 x UART (universal asynchronous receiver/transmitter),
• 2 × I²C (Inter-Integrated Circuit),
• 1 × I²S (Integrated Inter-IC Sound),
• LED PWM up to 6 channels,
• General DMA with - 3 x Tx + 3 x Rx,
• PWM for Motor control,
• 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0),
• 1 x Parallel IO controller (PARLIO),
• USB Serial/JTAG controller.

Security

• Secure boot.
• Flash encryption.
• 4096-bit OTP, up to 1792-bit for customers.
• Cryptographic hardware acceleration:
  • AES-128/256,
  • SHA accelerator,
  • RSA accelerator 3072 bit,
  • random number generator (RNG),
  • digital signature

<note important> Since the processor documentation is only available for the pre-production version, it may change in the final version <note>

https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32h2/esp32-h2-devkitm-1/user_guide.html