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--- en:multiasm:paarm:chapter_5_7 [2025/12/04 11:37] – [Interrupts] eriks.klavins
+++ en:multiasm:paarm:chapter_5_7 [2025/12/04 12:48] (current) – [Interrupts] eriks.klavins
@@ Line 178: / Line 178: @@
 There is no fixed number of interrupts available for the processor. The total number of available interrupts is defined by the Generic Interrupt Controller (GIC) implemented in the system. The Raspberry Pi 5 have a GIC-500 interrupt controller, and according to [[https://documentation-service.arm.com/static/5e9085b8c8052b1608761814?token=|ARM GIC architecture]], the Raspberry Pi 5 can have up to 1020 different interrupt IDs:
   * ID0..ID15 is used for Software Generated Interrupts (system calls)
-  * The next 16 IDs are used for Private Peripheral Interrupts for one single core
+  * The next 16 IDs are used for Private Peripheral Interrupts for a single core
+  * The rest of the IDs are for Shared Peripheral interrupts
+Practically, the Raspberry Pi 5 may have hundreds of interrupts from different sources in use, because the SoC chip BCM2712 have a lot of internal peripheral interrupts, the RP1 chip (the one that handles I/O lines and other peripherals on board) uses additional interrupts over PCIe bus. The Linux OS creates its own software interrupt, and finally, Linux combines them through the GIC.
+The interrupts can be disabled and enabled. For example:\\
+''<fc #800000>MSR</fc> DAIFCLR, <fc #ffa500>#2</fc><fc #6495ed> @ enable IRQ (interrupt request)</fc>''\\
+''<fc #800000>MSR</fc> DAIFCLR,<fc #ffa500> #1</fc><fc #6495ed> @ Enable FIQ</fc>''\\
+''<fc #800000>MSR</fc> DAIFSET, <fc #ffa500>#2</fc><fc #6495ed> @ disable IRQ</fc>''
+** The Stack Pointer and Interrupt Handling **
+When an interrupt or exception occurs, the processor automatically saves the minimal state. It then switches to the stack pointer associated with the current exception level. The interrupt handler can safely use the stack at that level without overwriting user or kernel data. For example, when an IRQ occurs at EL1, the CPU switches from the user’s stack (SP_EL0) to the kernel’s stack (SP_EL1). This change is invisible to user code and helps isolate privilege levels.
+Inside an interrupt handler, the code must save and restore any registers it modifies. A minimal handler might look like this:\\
+''irq_handler: <fc #6495ed>@ the label for the interrupt handler</fc>''\\
+''<fc #800000>STP</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, [<fc #008000>SP</fc>, <fc #ffa500>#-16</fc>]**<fc #6495ed>!</fc>**''\\
+''<fc #6495ed>@ Handle the interrupt (event)</fc>''\\
+''<fc #800000>LDP</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, [<fc #008000>SP</fc>], <fc #ffa500>#16</fc>''\\
+''<fc #800000>ERET</fc> <fc #6495ed>@ retorn from innetrupt (exception) handler</fc>''
+Here, the stack pointer ensures the handler has a private area to store data safely, even if multiple interrupts occur.
+<codeblock code_label>
+<caption>Simple examples of interrupt handlers</caption>
+<code>
+irq_el1_handler:
+    @ Save registers
+    STP X0, X1, [SP, #-16]!
+    STP X2, X3, [SP, #-16]!
+    @ Acknowledge interrupt (example for GIC)
+    MRS X0, ICC_IAR1_EL1       @ Read interrupt ID
+    CMP X0, #1020              @ Spurious?
+    BEQ irq_done
+    @ Handle interrupt (custom code here)
+    BL handle_device_irq
+    @ Signal end of interrupt
+    MSR ICC_EOIR1_EL1, X0
+irq_done:
+    @ Restore registers
+    LDP X2, X3, [SP], #16
+    LDP X0, X1, [SP], #16
+    ERET                       @ Return from exception
+</code>
+</codeblock>

en/multiasm/paarm/chapter_5_7.1764848232.txt.gz · Last modified: 2025/12/04 11:37 by eriks.klavins