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| en:multiasm:paarm:chapter_5_6 [2025/12/02 22:41] – eriks.klavins | en:multiasm:paarm:chapter_5_6 [2025/12/03 21:41] (current) – [Data copy/move instructions] eriks.klavins |
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| ====== Basic Instructions and Operations ====== | ====== Basic Instructions and Operations ====== |
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| ===== Instruction options ===== | Most of the program code consists of basic instructions that perform arithmetic operations, move data, perform logical operations, and control I/O digital lines, among other tasks. This section provides an introduction to the basic instructions of the ARM v8 instruction set. |
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| | ===== Arithmetical instructions ===== |
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| | All arithmetical operations are performed directly on the processor's registers. The most common instructions are the same ones we use every day to add two or more values together, subtract one value from another, multiply two values, or divide one value by another. In ARM assembly, the <fc #800000>ADD</fc>, <fc #800000>SUB</fc>, <fc #800000>MUL</fc>, and <fc #800000>DIV</fc> instructions perform the same function. All these instructions and other arithmetic instructions require that both values be placed in the registers. At this moment, we assume that all values in the registers are preloaded and ready to use, as demonstrated in the following instruction examples. |
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| | ''<fc #800000>ADD</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc> <fc #6495ed>@ adds the X1 and X2 values X0= X1 + X2</fc>'' |
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| | If the postfix S is added (ADDS), the status register is updated. \\ |
| | ''<fc #800000>ADDS</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc> <fc #6495ed>@ X0 = X1 + X2 Status register SR is updated</fc>''\\ |
| | ''<fc #800000>ADCS</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc> <fc #6495ed>@ X0 = X1 + X2 + C from the SR register. The status register SR is updated</fc>'' |
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| | A status update is helpful for the upcoming conditional instructions. ''<fc #800000>ADC</fc>'' or ''<fc #800000>ADCS</fc>'' are standard in multi-word arithmetic (e.g., 128-bit math). |
| | The ''<fc #800000>SUB</fc>'' and ''<fc #800000>DIV</fc>'' instructions rely on the order of the used variables to preserve a correct mathematical expression. |
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| | ''<fc #800000>SUB</fc> <fc #008000>X0</fc>, <fc #008000>X0</fc>, <fc #ffa500>#1</fc> <fc #6495ed>@ X0 = X0 – 1</fc>'' \\ |
| | ''<fc #800000>SUB</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #ffa500>#1</fc> <fc #6495ed>@ X0 = X1 – 1</fc>'' \\ |
| | ''<fc #800000>UDIV</fc> <fc #008000>X3</fc>, <fc #008000>X4</fc>, <fc #008000>X5</fc> <fc #6495ed>@ X3 = X4 / X5</fc>'' |
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| | All these arithmetical instructions have additional options, such as an optional shift of the second source operand. The <fc #800000>DIV</fc> instruction must have a prefix of S for Signed (<fc #800000>SDIV</fc>) or U for Unsigned (<fc #800000>UDIV</fc>) divide operations. Prefix S preserves the sign of the result, depending on the signs used for the operands. The prefix U always returns a positive value. |
| | Some instructions can be combined to achieve better computational performance. In such cases, the first arithmetic operation is performed on the second source register, and then the instruction's operation is performed. Such instructions are: ''<fc #800000>MADD</fc>'', ''<fc #800000>MSUB</fc>'', ''<fc #800000>SMADDL</fc>'', ''<fc #800000>SMSUBL</fc>'', ''<fc #800000>UMADDL</fc>'' and ''<fc #800000>UMSUBL</fc>''. Basically, all the listed instructions are ''<fc #800000>MADD</fc>'' and ''<fc #800000>MSUB</fc>'', but with different options. Let's look at ''<fc #800000>MADD</fc>'' and ''<fc #800000>MSUB</fc>'' instructions. |
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| | ''<fc #800000>MADD</fc> <fc #008000>X1</fc>, <fc #008000>X2</fc>, <fc #008000>X3</fc>, <fc #008000>X4</fc> <fc #6495ed>@ X1 = X4 + X2*X3</fc>''\\ |
| | ''<fc #800000>MSUB</fc> <fc #008000>X1</fc>, <fc #008000>X2</fc>, <fc #008000>X3</fc>, <fc #008000>X4</fc> <fc #6495ed>@ X1 = X4 - X2*X3</fc>'' |
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| | Before performing addition or subtraction, first multiply the registers X2 and X3 (the second and third operands given to the instruction), and then perform the addition or subtraction. The prefixes S and U define whether the result can be a signed value or only a positive value (unsigned value). The postfix L, like <fc #800000>SMSUBL</fc> or <fc #800000>UMADDL</fc>, specifies that only 32-bit register values are used when multiplying the second and third operands. The remaining operands are 64-bit register values. |
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| | The next ARM version, ARMv8.3, processors are built by default with a PAC (Pointer Authentication) system. Earlier architectures must have been checked to see whether the PAC system is available. This enables the system to protect against pointer errors or corruption and adds additional arithmetic instructions. The system's security level can be significantly increased by marking and checking pointers. PAC adds a signature to the pointer, allowing verification that it has not been tampered with before use. As a result, additional postfixes for the ''<fc #800000>ADD</fc>'' instruction, such as ''<fc #800000>ADDG</fc>'' and ''<fc #800000>ADDPT</fc>'', are added. While these operations are less common in simple programs, they are powerful tools when writing optimised and secure code. |
| | The ''<fc #800000>ADDG</fc>'' instruction means ''<fc #800000>ADD</fc>'' with Tag and is focused on pointers. The Tag is used to mark the pointer with a small identifier, allowing detection of pointer corruption or incorrect usage, among other options. Primarily, these instructions are used to authenticate pointers and ensure memory safety, for example, by tracking the boundaries of memory regions. |
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| | For example: ''<fc #800000>ADDG</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #ffa500>#16</fc>, <fc #ffa500>#5</fc>''\\ |
| | CPU takes the pointer from the ''<fc #008000>X1</fc>'' register and adds the first constant ''<fc #ffa500>#16</fc>'' multiplied by 16. The pointer ''<fc #008000>X0</fc>'' points to X1+256 and has a tag set to ''<fc #ffa500>#5</fc>'' or in binary form ''0101<sub>2</sub>''. ''<fc #008000>X0</fc>'' now points 256 bytes ahead of the memory address stored in the register ''<fc #008000>X1</fc>''. |
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| | Postfix PT adds support for pointer tagging or authentication. For example, ''<fc #800000>ADDPT</fc>'' adds authenticated pointers and preserves the PAC.\\ |
| | ''<fc #800000>ADDPT</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc>'' |
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| | The ''<fc #008000>X1</fc>'' register contains an authenticated pointer; this can be signed before with the ''<fc #800000>PACIA</fc>'' or other PAC-enabled instruction. Register ''<fc #008000>X2</fc>'' is the value, an offset from the ''<fc #008000>X1</fc>'' pointer. The result is a pointer with an offset and tagged with the same tag as the ''<fc #008000>X1</fc>'' pointer. Such arithmetic operations are also available for the ''<fc #800000>SUB</fc>'' instruction, but not available for the ''<fc #800000>MUL</fc>'' multiplication and ''<fc #800000>DIV</fc>'' division instructions. Such a system enables powerful system-level encryption. |
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| | ===== Instruction options ===== |
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| All assembly language types use similar mnemonics for arithmetic operations (some may require additional suffixes to identify some options for the instruction). A32 assembly instructions have specific suffixes to make commands executed conditionally, and those four most significant bits for many instructions give this ability. Unfortunately, there is no such option for A64, but there are special conditional instructions that we will describe later. | All assembly language types use similar mnemonics for arithmetic operations (some may require additional suffixes to identify some options for the instruction). A32 assembly instructions have specific suffixes to make commands executed conditionally, and those four most significant bits for many instructions give this ability. Unfortunately, there is no such option for A64, but there are special conditional instructions that we will describe later. |
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| We need to look at the instruction set documentation to determine the possible options for this instruction. The documentation lists three main differences between the <fc #800000>''ADD''</fc> instructions. Despite that, for the data manipulation instruction, the ‘S’ suffix can be added to update the status flags in the processor Status Register. | We need to look at the instruction set documentation to determine the possible options for this instruction. The documentation lists three main differences between the <fc #800000>''ADD''</fc> instructions. Despite that, for the data manipulation instruction, the ‘S’ suffix can be added to update the status flags in the processor Status Register. |
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| **1.The ADD and ADDS instructions with extended registers:** | **1.The ADD and ADDS instructions with extended registers:** |
| Similar options are available for many other ARMv8 instructions. The instruction set documentation may provide the necessary information to determine the possibilities and restrictions on instruction usage. By examining the instruction's binary form, it is possible to identify its capabilities and limitations. Assembler code is converted to binary, and the final binary code for the instruction depends on the provided operands and, if available, options. | Similar options are available for many other ARMv8 instructions. The instruction set documentation may provide the necessary information to determine the possibilities and restrictions on instruction usage. By examining the instruction's binary form, it is possible to identify its capabilities and limitations. Assembler code is converted to binary, and the final binary code for the instruction depends on the provided operands and, if available, options. |
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| | ===== Data copy/move instructions ===== |
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| | Remember, the processor primarily performs operations on data stored in registers. The data must be loaded into registers, and the result must be stored back in memory. For example, to change the value stored at a particular memory address, the ARM would require three instructions. First, the value from memory needs to be loaded into a register, then modified, and finally stored back into the memory from the register. Other architectures, such as x86, may allow operations on data directly in memory without register use. |
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| | The ''<fc #800000>LDR</fc>'' and ''<fc #800000>STR</fc>'' are basic instructions that load data from memory into a register and store data from a register into memory, respectively.\\ |
| | ''<fc #800000>LDR</fc> <fc #008000>X0</fc>, [<fc #008000>X1</fc>] <fc #6495ed>@ fill the register X0 with the data located at address stored in X1 register</fc>'' |
| | ''<fc #800000>STR</fc> <fc #008000>X1</fc>, [<fc #008000>X2</fc>] <fc #6495ed>@ store the content from register X1 into the memory at memory address given in the X2 register</fc>'' |
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| | The ''<fc #800000>LDR</fc>'' instruction loads the data from the memory address pointed to in the ''<fc #008000>X1</fc>'' register into the destination register ''<fc #008000>X0</fc>''. The register in square brackets, ''[<fc #008000>X1</fc>]'', is called the base register because its value is used as a memory address. Similarly, the STR instruction stores data from the ''<fc #008000>X1</fc>'' register to the memory location specified by the ''<fc #008000>X2</fc>'' register. |
| | If the register holding the memory address must be updated after each memory access, then post-indexed or pre-indexed modes can be used. Pre-indexed mode updates the base register before reading the value from memory. Post-indexed mode will update the base register after reading the value from memory. |
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| | ''<fc #800000>LDR</fc> <fc #008000>X0</fc>, [<fc #008000>X1</fc>, <fc #ffa500>#8</fc>]<fc #800080>**!**</fc> <fc #6495ed>@ Read the data located at address X1+8 and write into register X0 {PRE-INDEXED MODE X1 = X1 + 8}</fc>''\\ |
| | ''<fc #800000>LDR</fc> <fc #008000>X6</fc>, [<fc #008000>X7</fc>], <fc #ffa500>#16</fc> <fc #6495ed>@ loads a value to X6 register and then increases X7 by 16. {POST-INDEXED MODE X7 = X7 + 16}</fc>''\\ |
| | ''<fc #800000>STR</fc> <fc #008000>X6</fc>, [<fc #008000>X7</fc>], <fc #ffa500>#16</fc> <fc #6495ed>@ Store the value and then increase X7 by 16.</fc>'' |
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| | There is also a third option: using the offset value. This option must be used with caution because the offset value is multiplied by 8 (8 bytes).\\ |
| | ''<fc #800000>LDR</fc> <fc #008000>X0</fc>, [<fc #008000>X1</fc>, <fc #ffa500>#8</fc>] <fc #6495ed>@ Read the data located at address X1+8*8 and write into register X0 {X1 = X1 + 8*8}</fc>'' |
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| | <note important>Note that the exclamation mark after the square bracket makes a significant difference in how the data is accessed.</note> |
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| | Load and store instructions have the most additional options, more than for the arithmetical and logical operations. For example, the ''<fc #800000>LDADD</fc>'' instruction combines a load and an arithmetic operation. This is a part of the so-called atomic operations. The ''<fc #800000>LDADD</fc>'' instruction atomically loads a value from memory, adds the value held in a register, and finally stores the result back in memory at a different location. NOTE that the registers used in this instruction must not be the same. This is something like what would be for the x86 architecture. Unfortunately, no other arithmetic operations are available besides addition.\\ |
| | ''<fc #800000>LDADD</fc> <fc #008000>W1</fc>, <fc #008000>W2</fc>, [<fc #008000>X0</fc>]'' \\ |
| | The register ''<fc #008000>X0</fc>'' holds a memory address. The data/value is loaded into the ''<fc #008000>W2</fc>'' register, and then the value is added to the ''<fc #008000>W1</fc>'' register value, after which the new value ''[<fc #008000>X0</fc>]+<fc #008000>W1</fc>'' is stored back into memory at the exact location pointed by ''[<fc #008000>X0</fc>]''. Basically, the ''<fc #008000>W2</fc>'' register now holds the ''[<fc #008000>X0</fc>]''- pointed data that was present before the ''<fc #008000>W1</fc>'' value was added. Similar instructions are available to perform atomic logic operations on the memory data. |
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| | To copy content from one register to another, the ''<fc #800000>MOV</fc>'' instruction is used. The ''<fc #800000>FMOV</fc>'' instruction can also copy floating-point values. These instructions allow typecasting a floating-point value to an integer and vice versa. Here are some independent instruction examples\\ |
| | ''<fc #800000>MOV</fc> <fc #008000>X1</fc>, <fc #008000>X0</fc> <fc #6495ed>@ X1 = X0 (64 bit register copy)</fc>''\\ |
| | ''<fc #800000>MOV</fc> <fc #008000>W1</fc>, <fc #008000>W0</fc> <fc #6495ed>@ W1 = W0 (32 bit register copy)</fc>''\\ |
| | ''<fc #800000>FMOV</fc> <fc #008000>S1</fc>, <fc #008000>S0</fc> <fc #6495ed>@ float → float (32-bit floating-point copy between vector registers)</fc>''\\ |
| | ''<fc #800000>FMOV</fc> <fc #008000>X0</fc>, <fc #008000>D1</fc> <fc #6495ed> @ FP64 → int64 (copy from vector register to general-purpose register)</fc>''\\ |
| | ''<fc #800000>FMOV</fc> <fc #008000>D2</fc>, <fc #008000>X3</fc> <fc #6495ed>@ int64 → FP64 (copy from general-purpose register to vector register)</fc>''\\ |
| | ''<fc #800000>MOV</fc> <fc #008000>V1</fc>.<fc #808000>16b</fc>, <fc #008000>V0</fc>.<fc #808000>16b</fc> <fc #6495ed>@ vector register copy one byte</fc>''\\ |
| | The ''<fc #800000>MOV</fc>'' instructions can also be used to write a value into the register immediately. In the following example, all instructions are executed one by one:\\ |
| | ''<fc #800000>MOV</fc> <fc #008000>X0</fc>, <fc #ffa500>#123</fc> <fc #6495ed>@ assign value 291 to the register</fc>''\\ |
| | ''<fc #800000>MOVZ</fc> <fc #008000>X0</fc>, <fc #ffa500>#0x1234</fc>, <fc #800080>LSL</fc> <fc #ffa500>#48</fc><fc #6495ed> @ X0 = 0x1234 0000 0000 0000. The X0 value gets overvritten</fc>''\\ |
| | ''<fc #800000>MOVK</fc> <fc #008000>X0</fc>, <fc #ffa500>#0xABCD</fc>, <fc #800080>LSL</fc> <fc #ffa500>#0</fc> <fc #6495ed>@ X0 = 0x1234 0000 0000 ABCD, if before instruction execution the register value was 0x1234 0000 0000 0000</fc>'' |
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| | ===== Data copy/move instructions ===== |
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| | These instructions do not work with values that require arithmetic operations. Still, they are mainly used to manipulate individual bits in registers, widely used to test or verify values, and to perform other functions. Basic logic instructions for AARCH64 are:\\ |
| | ''<fc #800000>AND</fc> <fc #008000>X0</fc>, <fc #008000>X1</fc>, <fc #008000>X2</fc> <fc #6495ed>@ logical AND between X1 and X2, result is stored in X0</fc>''\\ |
| | ''<fc #800000>ORR</fc> <fc #008000>X6</fc>, <fc #008000>X7</fc>, <fc #008000>X8</fc> <fc #6495ed>@ logical OR between X7 and X8, result is stored in X6</fc>''\\ |
| | ''<fc #800000>EOR</fc> <fc #008000>X12</fc>, <fc #008000>X13</fc>, <fc #008000>X14</fc> <fc #6495ed>@ logical XOR between X13 and X14, result is stored in X12</fc>''\\ |
| | ''<fc #800000>NEG</fc> <fc #008000>X24</fc>, <fc #008000>X25</fc> <fc #6495ed>@ logical NOT, X24 is set to inverted X25</fc>'' |
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| | Remember that most instructions, which operate with registers, can update the status register by adding the postfix S at the end of the instruction. Logical instructions are fundamental for low-level programming. These instructions allow taking control over bits and are widely used in system code, device drivers, and embedded systems. Some instructions can perform combined bitwise operations, like ''<fc #800000>ORN</fc>'', which performs an OR operation with the inverted second operand. |
