Data Types and Encoding

Many instructions have additional suffixes to identify the length of data used. As one of the examples for multiple data lengths, the load/store instructions will be used in this section

TABLE

Table

Overall, by the ARMv8.0, a new feature to the processor is added. In this section, the main focus is on endianness, and the feature named “FEAT_MixedEnd” from ARMv8 processors allows programmers to control the endianness of the memory. This means that the ARMv8 have implemented both little-endian and big-endian. For the Raspberry PI v5 running in AArch64, the higher exception layers control the endianness for the lower exception layer. For example, the code running in the Exception Level EL1 layer can control the endianness of the EL0 Exception Level. Note that if the Linux OS is already running on the Raspberry PI, then the kernel EL1 endianness should not be changed, because the OS is running on the EL1 layer, and now no OS can switch endianness at runtime. As both modes are supported in the ARMv8, there might be a need to figure out what settings are set for EL0 concerning endianness. The ID_AA64MMFR0_EL1 is an AArch64 Memory Model Feature register that holds information about endianness. For the program code in the register ID_AA64MMFR0_EL1 bits [11:8] indicate the endianness features for the whole CPU.

For example, in the register ID_AA64MMFR0_EL1, the BigEndEL0 bits indicate the support for mixed-endian at Exception Level EL0. If the value is nonzero, then The SCTLR_EL1.E0E register bit field is controlled through higher Exception Levels. Assuming that our designed code will be executed in Exception Level EL0, then … ←- {not finished}