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ESP32-S2 General Information

The Espressif ESP32-S2 family is a series of low power, single-core microcontrollers built on the Espressif IoT platform. They feature a highly integrated SoC (System on Chip) architecture, combining a CPU, WiFi connectivity, and various peripherals in a compact package. The ESP32-S2 chips are designed for application in IoT, smart home devices, wearables and more, offering enhanced security features, low power consumption, and support for various communication protocols. These microcontrollers are known for their cost-effectiveness and capabilities of connected devices. ESP32-S2 SoC is based on Xtensa single core 32-bit LX7 microcontroler with additional ultra low power (ULP) coprocessor with Wifi 2.4GHz radio and numerals peripherals. For now the ESP32-S2 series includes the following chips in mass production:

  • ESP32-S2(Figure 1) ,
  • ESP32-S2F(Figure 2) ,
Figure 1: ESP32-S2.
Figure 2: ESP32-S2F.
ESP32-S2 Architecture Overview

(Figure 3) shows functional block diagram of ESP32-S2 chip[1]. Main common features of the ESP32-S2 are:

Processors

  • Main processor: • Xtensa® single-core 32-bit LX7 microprocessor, up to 240 MHz
    • Cores: 1
  • Ultra low power co-processor:
    • Cores: 1

Wireless connectivity

  • WiFi: 802.11 b/g/n/(802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode.

Memory: Internal memory

  • ROM: 128 KiB (for booting and core functions).
  • SRAM: 320 KiB (for data and instruction).
  • RTC SRAM: 16 KiB (for data storage and main CPU during RTC Boot from the deep-sleep mode).
  • Embedded flash
    • 0 MiB (ESP32-S2, ESP32-S2R2 chips),
    • 2 MiB (ESP32-S2FH2 chip),
    • 4 MiB (ESP32S2FH4, ESP32FN4R2 chips).
  • Embedded PSRAM
    • 0 MiB (ESP32-S2, ESP32-S2FH2, ESP32S2FH4 chips ),
    • 2 MiB (ESP32FN4R2, ESP32-S2R2 chips ).

Peripheral Input/Output

  • 43 programmable GPIOs
  • 2 × I²C (Inter-Integrated Circuit.
  • 2 x UART (universal asynchronous receiver/transmitter).
  • 4 × SPI (Serial Peripheral Interface).
  • 1 × I²S (Integrated Inter-IC Sound).
  • 1 x RMT (TX/RX).
  • Motor PWM (pulse width modulation).
  • LED PWM up to 8 channels.
  • DMA controller
  • 1 x TWAI controller compatible with CAN Spec. 2.0
  • 4 x pulse counters,
  • 1 x full speed USB OTG,
  • 1 x DVP 8/16 camera interface (I2S),
  • 1 x LCD serial interface (SPI)
  • 1 x LCD parallel interface

Analog interfaces

  • 2 x 13-bit ADCs up to 20 channels
  • 2 x 8-bit DACs
  • 14 x touch sensing GPIO
  • 1 x temperature sensor

Security

  • Secure boot.
  • Flash encryption.
  • IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI.
  • 4096-bit OTP, up to 1792-bit for customers.
  • Cryptographic hardware acceleration:
    • AES-128/192/256,
    • HMAC,
    • RSA,
    • random number generator (RNG).
Figure 3: ESP32-S2 Functional block diagram
ESP32-S2 Modules

The company also produces ready-made modules for easier implementation in user systems. These modules combines ESP32-S2 microcontroller and additional components mounted on PCB with EM shield [2](Table 1):

Table 1: Espressif ESP32-S2 modules
ModuleChip EmbeddedDimensions (mm)PinsFlash (MiB)PSRAM (MiB)AntennaDevelopment Board
ESP32-S2-MINI-2 (Figure 4) ESP32-S2FH4
ESP32-S2FN4R2
15.4×20×2.46540,2PCB ESP32-S2-DevKitM-1
ESP32-S2-MINI-2U ESP32-S2FH4
ESP32-S2FN4R2
15.4×15.4×2.46540,2IPEX ESP32-S2-DevKitM-1
ESP32-S2-SOLO-2 (Figure 5) ESP32-S2
ESP32-S2R2
18×25.5×3.14140,2PCB ESP32-S2-DevKitC-1
ESP32-S2-SOLO-2U ESP32-S2
ESP32-S2R2
18×19.2×3.24140,2IPEX ESP32-S2-DevKitC-1
ESP32-S2-MINI-1 ESP32-S2FH4
ESP32-S2FN4R2
15.4×20×2.4654 0,2PCB ESP32-S2-DevKitM-1
ESP32-S2-MINI-1U (Figure 6) ESP32-S2FH4
ESP32-S2FN4R2
15.4×15.4×2.46540,2IPEXESP32-S2-DevKitM-1
ESP32-S2-SOLO ESP32-S2
ESP32-S2R2
18×25.5×3.1404,8,160,2PCB ESP32-S2-DevKitC-1
ESP32-S2-SOLO-U ESP32-S2
ESP32-S2R2
18×19.2×3.2404,8,160,2IPEXESP32-S2-DevKitC-1


Figure 4: ESP32-S2-mini2.
Figure 5: ESP32-S2-solo2
Figure 6: ESP32-S2-mini-1U.
ESP32-S2 Development Kits

For convenience, use by users of all skill levels Espressif produces entry-level development boards using the ESP32-S2 SOCs. This boards integrates complete Wi-Fi functions. Most of the ESP32-S2 I/O pins are broken out to the pin headers on both sides for easy interfacing. Users can either connect peripherals with jumper wires or mount development kit on a breadboard. Many different companies offer ready-made boards with processors. The original Espressif best known small development boards are:

  • ESP32-S2-DevkitM [3](Figure 7) ,
  • ESP32-S2-DevkitC [4](Figure 8) ,
Figure 7: ESP32-S2-DevkitM
Figure 8: ESP32-S2-DevkitC

ESP32-S3 General Information

The ESP32-S3[5,6] is an advanced version within Espressif S family, offering improved performance and expanded capabilities compared to its predecessors. ESP32-S3 is a MCU with dual core 32-bit Xtensa LX7 microprocessor and dual ULP coprocessors with Wifi 2.4 GHz and Bluetooth LE radio and numerous usefull peripherals. ESP32-S3 offer enhanced processing power, lower power consumption and improved features for IoT and wireless connectivity applications. ESP32-S3 is designed for mobile systems, Industrial&Home Automation, Health Care devices, Touch and Proximity Sensing, wearable electronics, and Internet-of-Things (IoT) applications. In addition ESP32-S3 includes support for vector instructions in the MCU, which provides acceleration for neural network computing and signal processing workloads. For now the ESP32-S3 family includes the following chips in mass production:

  • ESP32-S3(Figure 9) ,
  • ESP32-S3-Pico-1(Figure 10)
Figure 9: ESP32-S3.
Figure 10: ESP32-S3-PICO-1.
ESP32-S3 Architecture Overview

(Figure 11) shows functional block diagram of ESP32-S3 chip. ESP32-S3 Main common features of the ESP32-S3 are:

Processors

  • Main processor: • Xtensa® dual-core 32-bit LX7 microprocessor, up to 240 MHz
    • Cores: 2
  • Ultra low power co-processor:
    • Cores: 2
    • ULP-RISC-V coprocessor - based onRISC-V instruction set architecture,
      • Support for RV32IMC instruction set,
      • Thirty-two 32-bit general-purpose registers,
      • 32-bit multiplier and divider,
      • Support for interrupts,
      • Booted by the CPU, its dedicated timer, or RTC GPIO
    • ULP-FSM coprocessor - based on finite state machine.
      • Support for common instructions including arithmetic, jump, and program control instructions,
      • Support for on-board sensor measurement instructions,
      • Booted by the CPU, its dedicated timer, or RTC GPIO

Wireless connectivity

  • WiFi: 802.11 b/g/n/mc (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode.
  • Bluetooth:
    • Low Energy Bluetooth 5, Bluetooth mesh
    • Speed 125kbps, 500 kbps, 1 Mbps, 2 Mbps
    • Internal sharing antenna with WiFi

Memory: Internal memory

  • ROM: 384 KiB (for booting and core functions).
  • SRAM: 512 KiB (for data and instruction).
  • RTC SRAM: 16 KiB (for data storage and main CPU during RTC Boot from the deep-sleep mode).
  • Embedded flash
    • 0 MiB (ESP32-S3, ESP32-S3R2, ESP32-S3R8, ESP32-S3R8V chips),
    • 4 MiB (ESP32-S3FH4R2 chip),
    • 8 MiB (ESP32-S3FN8 chip).
  • Embedded PSRAM
    • 0 MiB (ESP32-S3, ESP32-S3FN8 chips ),
    • 2 MiB (ESP32-S3R2, ESP32-S3FH4R2 chips ),
    • 8 MiB (ESP32-S3R8, ESP32-S3R8V chips ).

Peripheral Input/Output

  • 45 programmable GPIOs
  • 2 × I²C (Inter-Integrated Circuit.
  • 3 x UART (universal asynchronous receiver/transmitter).
  • 4 × SPI (Serial Peripheral Interface).
  • 2 × I²S (Integrated Inter-IC Sound).
  • 1 x RMT (TX/RX).
  • Motor PWM (pulse width modulation).
  • LED PWM up to 8 channels.
  • DMA controller with 5 transmit and 5 receive channels,
  • 1 x TWAI controller compatible with CAN Spec. 2.0
  • 4 x pulse counters,
  • 1 x full speed USB OTG,
  • 1 × USB Serial/JTAG controller,
  • 1 x DVP 8/16 camera interface (I2S),
  • 1 x LCD parallel interface,
  • 1 × SD/MMC host controller.

Analog interfaces

  • 2 x 12-bit ADCs up to 20 channels
  • 14 x touch sensing GPIO
  • 1 x temperature sensor

Low power management

  • Power Management Unit with five power modes
  • Ultra-Low-Power (ULP) coprocessors

Security

  • Secure boot.
  • Flash encryption.
  • IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI.
  • 4096-bit OTP, up to 1792-bit for customers.
  • Cryptographic hardware acceleration:
    • AES-128/192/256,
    • Hash (FIPS PUB 180-4)
    • HMAC,
    • RSA,
    • Digital signature,
    • random number generator (RNG).
Figure 11: ESP32-S3 Functional block diagram

ESP32-S3-PICO-1 has all function of ESP32-S3 but integrates all peripheral components, including a crystal oscillator, decoupling capacitors, SPI flash/PSRAM, and RF matching links, within a single package. (Figure 12) shows functional block diagramm of ESP32-S3-PICO-1 chip.

Figure 12: ESP32-S3-PICO-1 Functional block diagram
ESP32-S3 Modules

The company also produces ready-made modules[7,8,9]for easier implementation in user systems. These modules combines ESP32-S2 microcontroller, antenna and additional components mounted on PCB with EM shield [10] (Table 2):

Table 2: Espressif ESP32-S3 modules
ModuleChip EmbeddedDimensions (mm)PinsFlash (MiB)PSRAM (MiB)AntennaDevelopment Board
ESP32-S3-WROOM-1 (Figure 13) ESP32-S3
ESP32-S3R2 \\ESP32-S3R8
18×25.5×3.1414,8,160,2,8PCB ESP32-S3-DevKitC-1
ESP32-S3-DevKitC-1
ESP32-S3-BOX-3
ESP32-S3-BOX
ESP32-S3-EYE
ESP32-S3-Korvo-1
ESP32-S3-Korvo-2
ESP32-S3-LCD-Ev-Board
ESP32-S3-WROOM-1U ESP32-S3
ESP32-S3R2
ESP32-S3R8
18×19.2×3.2414,8,160,2,8IPEX ESP32-S3-DevKitC-1
ESP32-S3-WROOM-2 (Figure 14) ESP32-S3R8V 18×25.5×3.14116,328PCB ESP32-S3-DevKitC-1
ESP32-S3-MINI-1 (Figure 15) ESP32-S3FN8
ESP32-S3FH4R2
15.4×15.4×2.4658 N/A PCBESP32-S3-DevKitM-1
ESP32-S3-MINI-1U ESP32-S3FN8
ESP32-S3FH4R2
15.4×15.4×2.4658 N/AIPEXESP32-SM-DevKitM-1


Figure 13: ESP32-S3-Wroom-1/1U.
Figure 14: ESP32-S3-Wroom-2.
Figure 15: ESP32-S3-Wroom-1/1U.
ESP32-S3 Development Kits

To facilitate the use of ESP32-S3, Espressif and other companies produce different development kits to suit different needs and present different processor functions. The original Espressif best known small development boards are:

  • ESP32-S3-DevkitM,
  • ESP32-S3-DevkitC,
  • ESP32-S3-BOX-3,
  • ESP32-S3-BOX,
  • ESP32-S3-EYE,
  • ESP32-S3-Korvo-1,
  • ESP32-S3-Korvo-2,
  • ESP32-S3-LCD-Ev-Board

For the purposes of this book, we present only a few the most popular, universal for various applications, development boards:

  • ESP32-S3-DevkitM(Figure 16) ,
  • ESP32-S3-DevkitC(Figure 17) ,
  • Waveshare ESP32-PICO-1[11] (Figure 18),
  • M5Stamp-S3[12] (Figure 19).
Figure 16: ESP32-S3-DevkitM
Figure 17: ESP32-S3-DevkitC
Figure 18: Waveshare ESP32-S3-PICO-1
Figure 19: M5Stamp-S3 with pin headers

ESP32-S2&S3 chip comparison

Table 3 provides a brief comparison of the most important features of the ESP32-S2 & ESP32-S3 systems[13]

Table 3: ESP32-S2 & ESP32-S3 family brief comparison
FeatureESP32 SeriesESP32-S2 SeriesESP32-S3 Series
Launch year201620202020
CoreXtensa® dual-/single core 32-bit LX6Xtensa® single-core 32-bit LX7Xtensa® dual-core 32-bit LX7
Wi-Fi protocols802.11 b/g/n, 2.4 GHz802.11 b/g/n, 2.4 GHz802.11 b/g/n, 2.4 GHz
Bluetooth®Bluetooth v4.2 BR/EDR and Bluetooth Low Energy✖️Bluetooth 5.0
Typical frequency240 MHz (160 MHz for ESP32-S0WD)240 MHz240 MHz
SRAM520 KB320 KB512 KB
ROM448 KB for booting and core functions128 KB for booting and core functions384 KB for booting and core functions
Embedded flash2 MB, 4 MB, or none, depending on variants2 MB, 4 MB, or none, depending on variants8 MB or none, depending on variants
External flashUp to 16 MB device, address 11 MB + 248 KB each timeUp to 1 GB device, address 11.5 MB each timeUp to 1 GB device, address 32 MB each time
External RAMUp to 8 MB device, address 4 MB each timeUp to 1 GB device, address 11.5 MB each timeUp to 1 GB device, address 32 MB each time
Cache✔️ Two-way set associative✔️ Four-way set associative, independent instruction cache and data cache✔️ Four-way or eight-way set associative for instruction cache; four-way set associative for data cache, 32-bit data/instruction bus width
Peripherals
ADCTwo 12-bit, 18 channelsTwo 12-bit, 20 channelsTwo 12-bit SAR ADCs, 20 channels
DACTwo 8-bit channelsTwo 8-bit channels✖️
TimersFour 64-bit general-purpose timers, and three watchdog timersFour 64-bit general-purpose timers, and three watchdog timersFour 54-bit general-purpose timers, and three watchdog timers
Temperature sensor✖️11
Touch sensor101414
Hall sensor1✖️✖️
GPIO344345
SPI444
LCD interface111
UART32 13
I2C222
I2S2, can be configured to operate with 8/16/32/40/48-bit resolution as an input or output channel.1, can be configured to operate with 8/16/24/32/48/64-bit resolution as an input or output channel.2, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel.
Camera interface111
DMADedicated DMA to UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT, and Wi-FiDedicated DMA to UART, SPI, AES, SHA, I2S, and ADC ControllerGeneral-purpose, 5 TX channels, 5 RX channels
RMT8 channels4 channels 1, can be configured to TX/RX channels8 channels 2, 4 TX channels, 4 RX channels
Pulse counter8 channels4 channels 14 channels 1
LED PWM16 channels8 channels 18 channels 1
MCPWM2, six PWM outputs✖️2, six PWM outputs
USB OTG✖️11
TWAI® controller (compatible with ISO 11898-1)111
SD/SDIO/MMC host controller1✖️1
SDIO slave controller1✖️✖️
Ethernet MAC1✖️✖️
ULPULP FSMPicoRV32 core with 8 KB SRAM, ULP FSMPicoRV32 core with 8 KB SRAM, ULP FSM
Debug Assist✖️✖️✖️
Security
Secure boot✔️✔️ Faster and safer, compared with ESP32✔️ Faster and safer, compared with ESP32
Flash encryption✔️✔️ Support for PSRAM encryption. Safer, compared with ESP32✔️ Support for PSRAM encryption. Safer, compared with ESP32
OTP1024-bit4096-bit4096-bit
AES✔️ AES-128, AES-192, AES-256 (FIPS PUB 197)✔️ AES-128, AES-192, AES-256 (FIPS PUB 197); DMA support✔️ AES-128, AES-256 (FIPS PUB 197); DMA support
HASHSHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4)SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA supportSHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support
RSAUp to 4096 bitsUp to 4096 bitsUp to 4096 bits
RNG✔️✔️✔️
HMAC✖️✔️✔️
Digital signature✖️✔️✔️
XTS✖️✔️ XTS-AES-128, XTS-AES-256✔️ XTS-AES-128, XTS-AES-256
Other
Deep-sleep (ULP sensor-monitored pattern)100 μA (when ADC work with a duty cycle of 1%)22 μA (when touch sensors work with a duty cycle of 1%)TBD
SizeQFN48 5*5, 6*6, depending on variantsQFN56 7*7QFN56 7*7

- Note 1: Reduced chip area compared with ESP32

  1. Note 2: Reduced chip area compared with ESP32 and ESP32-S2
  2. Note 3: Die size: ESP32-S2 < ESP32-S3 < ESP32




en/iot-open/hardware2/esp32s.1699178072.txt.gz · Last modified: 2023/11/05 09:54 by jpaduch
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