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en:iot-open:hardware2:esp32s [2023/11/05 09:53] – jpaduch | en:iot-open:hardware2:esp32s [2024/05/27 11:15] (current) – pczekalski | ||
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- | ===ESP32-S2 General Information=== | + | ======ESP32-Sx Family====== |
- | The Espressif ESP32-S2 family is a series of low power, single-core microcontrollers built on the Espressif IoT platform. They feature a highly integrated SoC (System on Chip) architecture, | + | {{: |
- | For now the ESP32-S2 series includes the following chips in mass production: | + | ===== ESP32-S2 ===== |
- | * ESP32-S2(Figure | + | |
- | * ESP32-S2F(Figure | + | ==ESP32-S2 General Information== |
+ | The Espressif ESP32-S2 family is a series of low-power, single-core microcontrollers built on the Espressif IoT platform. They feature a highly integrated SoC (System on Chip) architecture, | ||
+ | For now, the ESP32-S2 series includes the following chips in mass production: | ||
+ | * ESP32-S2 (figure | ||
+ | * ESP32-S2F (figure | ||
| | ||
<figure esp32_s2> | <figure esp32_s2> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_s2f> | <figure esp32_s2f> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
== ESP32-S2 Architecture Overview == | == ESP32-S2 Architecture Overview == | ||
- | (Figure {{ref> | + | Figure {{ref> |
**Processors** | **Processors** | ||
* **Main processor: | * **Main processor: | ||
* **Cores**: 1 | * **Cores**: 1 | ||
- | * **Ultra low power co-processor:** | + | * **Ultra low power coprocessor:** |
* **Cores**: 1 | * **Cores**: 1 | ||
**Wireless connectivity** | **Wireless connectivity** | ||
Line 27: | Line 31: | ||
**Memory: Internal memory** | **Memory: Internal memory** | ||
- | * **ROM:** 128 KiB (for booting and core functions). | + | * **ROM:** 128 kB (for booting and core functions), |
- | * **SRAM:** 320 KiB (for data and instruction). | + | * **SRAM:** 320 kB (for data and instruction), |
- | * **RTC SRAM:** 16 KiB (for data storage and main CPU during RTC Boot from the deep-sleep mode). | + | * **RTC SRAM:** 16 kB (for data storage and main CPU during RTC Boot from the deep-sleep mode), |
- | * **Embedded flash** | + | * **Embedded flash:** |
- | * 0 MiB (ESP32-S2, ESP32-S2R2 chips), | + | * 0 MB (ESP32-S2, ESP32-S2R2 chips), |
- | * 2 MiB (ESP32-S2FH2 chip), | + | * 2 MB (ESP32-S2FH2 chip), |
- | * 4 MiB (ESP32S2FH4, | + | * 4 MB (ESP32S2FH4, |
- | * **Embedded PSRAM** | + | * **Embedded PSRAM:** |
- | * 0 MiB (ESP32-S2, ESP32-S2FH2, | + | * 0 MB (ESP32-S2, ESP32-S2FH2, |
- | * 2 MiB (ESP32FN4R2, | + | * 2 MB (ESP32FN4R2, |
**Peripheral Input/ | **Peripheral Input/ | ||
- | * 43 programmable GPIOs | + | * 43 programmable GPIOs, |
- | * 2 × I²C (Inter-Integrated Circuit. | + | * 2 × I²C (Inter-Integrated Circuit, |
- | * 2 x UART (universal asynchronous receiver/ | + | * 2 x UART (universal asynchronous receiver/ |
- | * 4 × SPI (Serial Peripheral Interface). | + | * 4 × SPI (Serial Peripheral Interface), |
- | * 1 × I²S (Integrated Inter-IC Sound). | + | * 1 × I²S (Integrated Inter-IC Sound), |
- | * 1 x RMT (TX/RX). | + | * 1 x RMT (TX/RX), |
- | * Motor PWM (pulse width modulation). | + | * Motor PWM (pulse width modulation), |
- | * LED PWM up to 8 channels. | + | * LED PWM up to 8 channels, |
- | * DMA controller | + | * DMA controller, |
- | * 1 x TWAI controller compatible with CAN Spec. 2.0 | + | * 1 x TWAI controller compatible with CAN Spec. 2.0, |
* 4 x pulse counters, | * 4 x pulse counters, | ||
- | * 1 x full speed USB OTG, | + | * 1 x full-speed USB OTG, |
* 1 x DVP 8/16 camera interface (I2S), | * 1 x DVP 8/16 camera interface (I2S), | ||
- | * 1 x LCD serial interface (SPI) | + | * 1 x LCD serial interface (SPI), |
- | * 1 x LCD parallel interface | + | * 1 x LCD parallel interface. |
**Analog interfaces** | **Analog interfaces** | ||
- | * 2 x 13-bit ADCs up to 20 channels | + | * 2 x 13-bit ADCs up to 20 channels, |
- | * 2 x 8-bit DACs | + | * 2 x 8-bit DACs, |
- | * 14 x touch sensing GPIO | + | * 14 x touch sensing GPIO, |
- | * 1 x temperature sensor | + | * 1 x temperature sensor. |
**Security** | **Security** | ||
- | * Secure boot. | + | * Secure boot, |
- | * Flash encryption. | + | * Flash encryption, |
- | * IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI. | + | * IEEE 802.11 standard security features |
- | * 4096-bit OTP, up to 1792-bit for customers. | + | * 4096-bit OTP, up to 1792-bit for customers, |
* Cryptographic hardware acceleration: | * Cryptographic hardware acceleration: | ||
* AES-128/ | * AES-128/ | ||
Line 73: | Line 77: | ||
<figure esp32s2_functions> | <figure esp32s2_functions> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
Line 79: | Line 83: | ||
| | ||
== ESP32-S2 Modules == | == ESP32-S2 Modules == | ||
- | The company also produces ready-made modules for easier implementation in user systems. | + | The company also produces ready-made modules for easier implementation in user systems. These modules combines ESP32-S2 microcontroller and additional components mounted on PCB with EM shield ((https:// |
<table esp32s2_modules> | <table esp32s2_modules> | ||
< | < | ||
- | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**Flash (MiB)**^**PSRAM (MiB)**^**Antenna**^**Development Board**^ | + | ^ **Module** |
- | |ESP32-S2-MINI-2 (Figure | + | | ESP32-S2-MINI-2 (figure |
- | |ESP32-S2-MINI-2U| ESP32-S2FH4 \\ ESP32-S2FN4R2 |15.4×15.4×2.4|65|4|0, | + | | ESP32-S2-MINI-2U |
- | |ESP32-S2-SOLO-2 (Figure | + | | ESP32-S2-SOLO-2 (figure |
- | |ESP32-S2-SOLO-2U| ESP32-S2 \\ ESP32-S2R2|18×19.2×3.2|41|4|0, | + | | ESP32-S2-SOLO-2U |
- | |ESP32-S2-MINI-1 | ESP32-S2FH4 \\ ESP32-S2FN4R2|15.4×20×2.4|65|4 |0,2|PCB |ESP32-S2-DevKitM-1| | + | | ESP32-S2-MINI-1 |
- | |ESP32-S2-MINI-1U (Figure | + | | ESP32-S2-MINI-1U (figure |
- | |ESP32-S2-SOLO | + | | ESP32-S2-SOLO |
- | |ESP32-S2-SOLO-U | ESP32-S2 \\ ESP32-S2R2 |18×19.2×3.2|40|4, | + | | ESP32-S2-SOLO-U |
- | \\ | + | |
</ | </ | ||
| | ||
<figure esp32_S2_mini2> | <figure esp32_S2_mini2> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
| | ||
<figure esp32_S2_solo2> | <figure esp32_S2_solo2> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
<figure esp32_S2_mini1> | <figure esp32_S2_mini1> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
== ESP32-S2 Development Kits == | == ESP32-S2 Development Kits == | ||
- | For convenience, | + | For convenience, |
- | * ESP32-S2-DevkitM ((https:// | + | * ESP32-S2-DevkitM ((https:// |
- | * ESP32-S2-DevkitC ((https:// | + | * ESP32-S2-DevkitC ((https:// |
<figure esp32_S2_devkitm> | <figure esp32_S2_devkitm> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
<figure esp32_S2_devkitc> | <figure esp32_S2_devkitc> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
+ | ===== ESP32-S3 ===== | ||
- | === ESP32-S3 General Information | + | == ESP32-S3 General Information == |
- | The ESP32-S3((https:// | + | The ESP32-S3((https:// |
- | * ESP32-S3(Figure | + | * ESP32-S3 (figure |
- | * ESP32-S3-Pico-1(Figure | + | * ESP32-S3-Pico-1 (figure |
| | ||
<figure esp32_s3> | <figure esp32_s3> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_s3pico1> | <figure esp32_s3pico1> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
== ESP32-S3 Architecture Overview == | == ESP32-S3 Architecture Overview == | ||
- | (Figure {{ref> | + | Figure {{ref> |
**Processors** | **Processors** | ||
- | * **Main processor: | + | * **Main processor: |
* **Cores**: 2 | * **Cores**: 2 | ||
- | * **Ultra low power co-processor:** | + | * **Ultra low power coprocessor:** |
* **Cores**: 2 | * **Cores**: 2 | ||
- | * ULP-RISC-V coprocessor - based onRISC-V instruction set architecture, \\ | + | * ULP-RISC-V coprocessor - based on RISC-V instruction set architecture: \\ |
* Support for RV32IMC instruction set, | * Support for RV32IMC instruction set, | ||
* Thirty-two 32-bit general-purpose registers, | * Thirty-two 32-bit general-purpose registers, | ||
* 32-bit multiplier and divider, | * 32-bit multiplier and divider, | ||
* Support for interrupts, | * Support for interrupts, | ||
- | * Booted by the CPU, its dedicated timer, or RTC GPIO | + | * Booted by the CPU, its dedicated timer, or RTC GPIO. |
- | * ULP-FSM coprocessor - based on finite state machine. | + | * ULP-FSM coprocessor - based on finite state machine: |
- | * Support for common instructions including arithmetic, jump, and program control instructions, | + | * Support for common instructions, including arithmetic, jump, and program control instructions, |
* Support for on-board sensor measurement instructions, | * Support for on-board sensor measurement instructions, | ||
- | * Booted by the CPU, its dedicated timer, or RTC GPIO | + | * Booted by the CPU, its dedicated timer, or RTC GPIO. |
**Wireless connectivity** | **Wireless connectivity** | ||
* **WiFi:** 802.11 b/g/n/mc (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/ | * **WiFi:** 802.11 b/g/n/mc (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/ | ||
* **Bluetooth: | * **Bluetooth: | ||
- | * Low Energy Bluetooth 5, Bluetooth mesh | + | * Low Energy Bluetooth 5, Bluetooth mesh, |
- | * Speed 125kbps, 500 kbps, 1 Mbps, 2 Mbps | + | * Speed 125kbps, 500 kbps, 1 Mbps, 2 Mbps, |
- | * Internal sharing antenna with WiFi | + | * Internal sharing antenna with WiFi. |
- | **Memory: Internal memory** | + | **Memory: Internal memory:** |
- | * **ROM:** 384 KiB (for booting and core functions). | + | * **ROM:** 384 kB (booting and core functions), |
- | * **SRAM:** 512 KiB (for data and instruction). | + | * **SRAM:** 512 kB (for data and instruction), |
- | * **RTC SRAM:** 16 KiB (for data storage and main CPU during RTC Boot from the deep-sleep mode). | + | * **RTC SRAM:** 16 kB (for data storage and main CPU during RTC Boot from the deep-sleep mode), |
- | * **Embedded flash** | + | * **Embedded flash:** |
- | * 0 MiB (ESP32-S3, ESP32-S3R2, ESP32-S3R8, ESP32-S3R8V chips), | + | * 0 MB (ESP32-S3, ESP32-S3R2, ESP32-S3R8, ESP32-S3R8V chips), |
- | * 4 MiB (ESP32-S3FH4R2 chip), | + | * 4 MB (ESP32-S3FH4R2 chip), |
- | * 8 MiB (ESP32-S3FN8 chip). | + | * 8 MB (ESP32-S3FN8 chip). |
- | * **Embedded PSRAM** | + | * **Embedded PSRAM:** |
- | * 0 MiB (ESP32-S3, ESP32-S3FN8 chips ), | + | * 0 MB (ESP32-S3, ESP32-S3FN8 chips ), |
- | * 2 MiB (ESP32-S3R2, | + | * 2 MB (ESP32-S3R2, |
- | * 8 MiB (ESP32-S3R8, | + | * 8 MB (ESP32-S3R8, |
- | **Peripheral Input/ | + | **Peripheral Input/ |
- | * 45 programmable GPIOs | + | * 45 programmable GPIOs, |
- | * 2 × I²C (Inter-Integrated Circuit. | + | * 2 × I²C (Inter-Integrated Circuit, |
- | * 3 x UART (universal asynchronous receiver/ | + | * 3 x UART (universal asynchronous receiver/ |
- | * 4 × SPI (Serial Peripheral Interface). | + | * 4 × SPI (Serial Peripheral Interface), |
- | * 2 × I²S (Integrated Inter-IC Sound). | + | * 2 × I²S (Integrated Inter-IC Sound), |
- | * 1 x RMT (TX/RX). | + | * 1 x RMT (TX/RX), |
- | * Motor PWM (pulse width modulation). | + | * Motor PWM (pulse width modulation), |
- | * LED PWM up to 8 channels. | + | * LED PWM up to 8 channels, |
* DMA controller with 5 transmit and 5 receive channels, | * DMA controller with 5 transmit and 5 receive channels, | ||
- | * 1 x TWAI controller compatible with CAN Spec. 2.0 | + | * 1 x TWAI controller compatible with CAN Spec. 2.0, |
* 4 x pulse counters, | * 4 x pulse counters, | ||
- | * 1 x full speed USB OTG, | + | * 1 x full-speed USB OTG, |
* 1 × USB Serial/JTAG controller, | * 1 × USB Serial/JTAG controller, | ||
* 1 x DVP 8/16 camera interface (I2S), | * 1 x DVP 8/16 camera interface (I2S), | ||
Line 200: | Line 203: | ||
* 1 × SD/MMC host controller. | * 1 × SD/MMC host controller. | ||
- | **Analog interfaces** | + | **Analog interfaces:** |
- | * 2 x 12-bit ADCs up to 20 channels | + | * 2 x 12-bit ADCs up to 20 channels, |
- | * 14 x touch sensing GPIO | + | * 14 x touch sensing GPIO, |
- | * 1 x temperature sensor | + | * 1 x temperature sensor. |
- | ** Low power management** | + | ** Low power management:** |
- | * Power Management Unit with five power modes | + | * Power Management Unit with five power modes, |
- | * Ultra-Low-Power (ULP) coprocessors | + | * Ultra-low-power (ULP) coprocessors. |
- | **Security** | + | **Security:** |
- | * Secure boot. | + | * Secure boot, |
- | * Flash encryption. | + | * Flash encryption, |
- | * IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI. | + | * IEEE 802.11 standard security features |
- | * 4096-bit OTP, up to 1792-bit for customers. | + | * 4096-bit OTP, up to 1792-bit for customers, |
* Cryptographic hardware acceleration: | * Cryptographic hardware acceleration: | ||
* AES-128/ | * AES-128/ | ||
- | * Hash (FIPS PUB 180-4) | + | * Hash (FIPS PUB 180-4), |
* HMAC, | * HMAC, | ||
* RSA, | * RSA, | ||
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<figure esp32s3_functions> | <figure esp32s3_functions> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
- | ESP32-S3-PICO-1 has all function | + | ESP32-S3-PICO-1 has all the functions |
<figure esp32s3pico_functions> | <figure esp32s3pico_functions> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
| | ||
== ESP32-S3 Modules == | == ESP32-S3 Modules == | ||
- | The company also produces ready-made modules((https:// | + | The company also produces ready-made modules((https:// |
<table esp32s3_modules> | <table esp32s3_modules> | ||
< | < | ||
- | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**Flash (MiB)**^**PSRAM (MiB)**^**Antenna**^**Development Board**^ | + | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**Flash (MB)**^**PSRAM (MB)**^**Antenna**^**Development Board**^ |
- | |ESP32-S3-WROOM-1 (Figure | + | |ESP32-S3-WROOM-1 (figure |
|ESP32-S3-WROOM-1U| ESP32-S3 \\ ESP32-S3R2 \\ ESP32-S3R8 |18×19.2×3.2|41|4, | |ESP32-S3-WROOM-1U| ESP32-S3 \\ ESP32-S3R2 \\ ESP32-S3R8 |18×19.2×3.2|41|4, | ||
- | |ESP32-S3-WROOM-2 (Figure | + | |ESP32-S3-WROOM-2 (figure |
- | |ESP32-S3-MINI-1 (Figure | + | |ESP32-S3-MINI-1 (figure |
|ESP32-S3-MINI-1U | ESP32-S3FN8 \\ ESP32-S3FH4R2 |15.4×15.4×2.4|65|8 |N/ | |ESP32-S3-MINI-1U | ESP32-S3FN8 \\ ESP32-S3FH4R2 |15.4×15.4×2.4|65|8 |N/ | ||
- | \\ | + | </ |
- | </ | ||
- | | ||
<figure esp32_s3_wroom1> | <figure esp32_s3_wroom1> | ||
- | {{ : | + | {{ : |
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
| | ||
<figure esp32_s3_wroom2> | <figure esp32_s3_wroom2> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_s3_mini1> | <figure esp32_s3_mini1> | ||
- | {{ : | + | {{ : |
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
- | |||
== ESP32-S3 Development Kits == | == ESP32-S3 Development Kits == | ||
- | To facilitate the use of ESP32-S3, Espressif and other companies produce different development kits to suit different needs and present different processor functions. The original Espressif best known small development boards are: | + | To facilitate the use of ESP32-S3, Espressif and other companies produce different development kits to suit different needs and present different processor functions. The original Espressif best-known small development boards are: |
* ESP32-S3-DevkitM, | * ESP32-S3-DevkitM, | ||
* ESP32-S3-DevkitC, | * ESP32-S3-DevkitC, | ||
Line 275: | Line 275: | ||
* ESP32-S3-Korvo-1, | * ESP32-S3-Korvo-1, | ||
* ESP32-S3-Korvo-2, | * ESP32-S3-Korvo-2, | ||
- | * ESP32-S3-LCD-Ev-Board | + | * ESP32-S3-LCD-Ev-Board. |
- | For the purposes of this book, we present only a few the most popular, universal for various applications, development boards: | + | For this book, we present only a few of the most popular, universal for various applications development boards: |
- | * ESP32-S3-DevkitM(Figure | + | * ESP32-S3-DevkitM(figure |
- | * ESP32-S3-DevkitC(Figure | + | * ESP32-S3-DevkitC(figure |
- | * Waveshare ESP32-PICO-1((https:// | + | * Waveshare ESP32-PICO-1((https:// |
- | * M5Stamp-S3((https:// | + | * M5Stamp-S3((https:// |
<figure esp32_S3_devkitm> | <figure esp32_S3_devkitm> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
<figure esp32_S3_devkitc> | <figure esp32_S3_devkitc> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
<figure esp32_S3_pico1> | <figure esp32_S3_pico1> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
<figure esp32_S3_stamp> | <figure esp32_S3_stamp> | ||
- | {{ : | + | {{ : |
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
- | ===ESP32-S2& | + | ==ESP32-S2& |
- | Table {{ref> | + | Table {{ref> |
<table esp32s2s3> | <table esp32s2s3> | ||
Line 362: | Line 362: | ||
|Deep-sleep (ULP sensor-monitored pattern)|100 μA (when ADC work with a duty cycle of 1%)|22 μA (when touch sensors work with a duty cycle of 1%)|TBD| | |Deep-sleep (ULP sensor-monitored pattern)|100 μA (when ADC work with a duty cycle of 1%)|22 μA (when touch sensors work with a duty cycle of 1%)|TBD| | ||
|Size|QFN48 5*5, 6*6, depending on variants|QFN56 7*7|QFN56 7*7| | |Size|QFN48 5*5, 6*6, depending on variants|QFN56 7*7|QFN56 7*7| | ||
+ | |||
- **Note** 1: Reduced chip area compared with ESP32 \\ | - **Note** 1: Reduced chip area compared with ESP32 \\ | ||
- **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 \\ | - **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 \\ | ||
- **Note** 3: Die size: ESP32-S2 < ESP32-S3 < ESP32 \\ | - **Note** 3: Die size: ESP32-S2 < ESP32-S3 < ESP32 \\ | ||
- | \\ | ||
- | \\ \\ | ||
- | </ | ||
+ | </ | ||