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| en:iot-open:hardware2:esp32h [2023/10/25 08:21] – created pczekalski | en:iot-open:hardware2:esp32h [2024/05/27 11:09] (current) – [ESP32-H2] pczekalski | ||
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| - | === ESP32-H === | + | ======ESP32-Hx Family====== |
| - | <box #84b96a></box> | + | {{: |
| - | <box #84b96a></box> | + | =====ESP32-H2===== |
| + | |||
| + | ==ESP32-H2 General Information== | ||
| + | |||
| + | ESP32-H2 is a family of microcontrollers (SoC) that combines IEEE 802.15.4 connectivity with Bluetooth 5 (LE). The system does not have a Wi-Fi protocol, but Thread and Zigbee protocols are available. ESP32-H2 has been certified as a “Zigbee-Compliant Platform” and has officially become a “Thread-Certified 1.3.0 Component”. The SoC is powered by a single-core, | ||
| + | For now, the ESP32-H2 family documentation is available as preliminary information only. | ||
| + | |||
| + | == ESP32-H2 Architecture Overview == | ||
| + | Figure {{ref> | ||
| + | |||
| + | **Processors** | ||
| + | * **Main processor: | ||
| + | * **Cores**: 1 | ||
| + | |||
| + | |||
| + | **Wireless connectivity** | ||
| + | * **Bluetooth: | ||
| + | * ** 802.15.4-2015: | ||
| + | |||
| + | **Memory: Internal memory** | ||
| + | * **Embedded flash** | ||
| + | * **ROM:** 128 kB (for booting and core functions), | ||
| + | * **SRAM:** 320 kB (for data and instructions), | ||
| + | * **LP memory:** 4 KB of SRAM that can be accessed by the CPU. It can retain data in deep sleep mode, | ||
| + | * ** eFuse ** - 4 Kbit: 1792 bits are reserved for user data, such as encryption key and device ID. | ||
| + | |||
| + | **Peripheral Input/ | ||
| + | * 19 x GPIO, | ||
| + | * 2 x 12-bit ADCs (analog-to-digital converter) up to 5 channels, | ||
| + | * Internal temperature sensor, | ||
| + | * 3 × SPI (Serial Peripheral Interface), | ||
| + | * 2 x UART (universal asynchronous receiver/ | ||
| + | * 2 × I²C (Inter-Integrated Circuit), | ||
| + | * 1 × I²S (Integrated Inter-IC Sound), | ||
| + | * LED PWM up to 6 channels, | ||
| + | * General DMA with - 3 x Tx + 3 x Rx, | ||
| + | * PWM for Motor control, | ||
| + | * 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0), | ||
| + | * 1 x Parallel IO controller (PARLIO), | ||
| + | * USB Serial/JTAG controller. | ||
| + | |||
| + | **Security** | ||
| + | * Secure boot, | ||
| + | * Flash encryption, | ||
| + | * 4096-bit OTP, up to 1792-bit for customers, | ||
| + | * Cryptographic hardware acceleration: | ||
| + | * AES-128/ | ||
| + | * SHA accelerator, | ||
| + | * RSA accelerator 3072 bit, | ||
| + | * random number generator (RNG), | ||
| + | * digital signature. | ||
| + | |||
| + | <note important> | ||
| + | Since the processor documentation is only available for the pre-production version, it may change in the final version | ||
| + | </note> | ||
| + | |||
| + | <figure esp32h2_functions> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | ==ESP32-H2 Development Boards== | ||
| + | There are not many prototype kits with ESP32-H2 SOCs on the market yet. One of them is produced by the Espressif company itself: | ||
| + | * Espressif - ESP32-H2-DevkitM-1((https:// | ||
| + | |||
| + | <figure esp32h2_devkitm> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||