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en:iot-open:hardware2:esp32c [2023/11/12 13:40] – jpaduch | en:iot-open:hardware2:esp32c [2024/08/25 11:51] (current) – [ESP32-C6] pczekalski | ||
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- | ===ESP32-C2 General Information=== | + | ======ESP32-Cx Family====== |
+ | {{: | ||
+ | ==ESP32-C2 General Information== | ||
- | The ESP32-C2 (ESP8684) ((https:// | + | The ESP32-C2 (ESP8684) ((https:// |
The ESP32-C2 microcontrollers come with several distinctive features: | The ESP32-C2 microcontrollers come with several distinctive features: | ||
- | * RISC-V Core: The ESP32-C2 is based on the RISC-V architecture, | + | * RISC-V Core: The ESP32-C2 is based on the RISC-V architecture, |
* Connectivity: | * Connectivity: | ||
- | * Low Power Consumption: | + | * Low Power Consumption: |
* Rich Peripheral Interface Support: It includes a variety of peripherals such as UART, I2C, SPI, ADC, and more, making it versatile for different applications. | * Rich Peripheral Interface Support: It includes a variety of peripherals such as UART, I2C, SPI, ADC, and more, making it versatile for different applications. | ||
- | * Security Features: The ESP32-C2 family includes various security features | + | * Security Features: The ESP32-C2 family includes various security features, such as secure boot, flash encryption, secure storage, and cryptographic accelerators. |
- | * Compact Form Factor: The ESP32-C2 family is designed in a very compact form factor (4mm x 4mm), which is crucial for applications | + | * Compact Form Factor: The ESP32-C2 family is designed in a very compact form factor (4mm x 4mm), which is crucial for applications |
* Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | * Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | ||
- | For now the ESP32-C2 family includes the following chips in mass production (figure {{ref>esp32c2}}): | + | For now the ESP32-C2 family includes the following chips in mass production (figure {{ref>esp32_c2}}): |
- | * ESP8684 | + | * ESP8684. |
<figure esp32_c2> | <figure esp32_c2> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
+ | |||
+ | ===== ESP32-C2 ===== | ||
== ESP32-C2 Architecture Overview == | == ESP32-C2 Architecture Overview == | ||
- | (Figure {{ref> | + | Figure {{ref> |
**Processors** | **Processors** | ||
* **Main processor: | * **Main processor: | ||
* **Cores**: 1 up to 120 MHz, | * **Cores**: 1 up to 120 MHz, | ||
- | * External main crystal clock | + | * External main crystal clock, |
- | * External 32 kHz crystal oscillator for RTC or internal RC | + | * External 32 kHz crystal oscillator for RTC or internal RC. |
**Wireless connectivity** | **Wireless connectivity** | ||
- | * **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 72.2 Mbit/s) with simultaneous Infrastructure BSS Station mode/ | + | * **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 72.2 Mbit/s) with simultaneous Infrastructure BSS Station mode/ |
* **Bluetooth: | * **Bluetooth: | ||
**Memory: Internal memory** | **Memory: Internal memory** | ||
- | * **Embedded flash** | + | * **Embedded flash** |
- | * **ROM:** 576 KiB (for booting and core functions). | + | * **ROM:** 576 kB (for booting and core functions), |
- | * **SRAM:** 272 KiB (16KiB for cache). | + | * **SRAM:** 272 kB (16kB for cache), |
- | * ** eFuse ** - 1 Kbit -256 bits reserved for encryption key and device ID | + | * ** eFuse ** - 1 Kbit -256 bits reserved for encryption key and device ID. |
**Peripheral Input/ | **Peripheral Input/ | ||
- | * 14 x GPIO | + | * 14 x GPIO, |
* 3 × SPI (Serial Peripheral Interface), | * 3 × SPI (Serial Peripheral Interface), | ||
* 2 x UART (universal asynchronous receiver/ | * 2 x UART (universal asynchronous receiver/ | ||
* 1 × I²C Master (Inter-Integrated Circuit), | * 1 × I²C Master (Inter-Integrated Circuit), | ||
- | * LED PWM up to 6 channels. | + | * LED PWM up to 6 channels, |
- | * 1 x 12-bit ADCs (analog-to-digital converter) up to 5 channels, | + | * 1 x 12-bit ADCs (analogue-to-digital converter) up to 5 channels, |
- | * General DMA controller (GDMA), with 1 transmit | + | * General DMA controller (GDMA), with 1 transmit |
** Power Modes ** | ** Power Modes ** | ||
Line 55: | Line 59: | ||
**Security** | **Security** | ||
- | * Secure boot. | + | * Secure boot, |
- | * Flash encryption. | + | * Flash encryption, |
- | * 1024-bit OTP, up to 256-bit for customers. | + | * 1024-bit OTP, up to 256-bit for customers, |
* Cryptographic hardware acceleration: | * Cryptographic hardware acceleration: | ||
* SHA1/ | * SHA1/ | ||
Line 65: | Line 69: | ||
<figure esp32c2_functions> | <figure esp32c2_functions> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
- | For now the ESP32-C3 family includes the following chips in mass production (Table {{ref>esp32c3_chips}}): | + | For now the ESP32-C2 family includes the following chips in mass production (table {{ref>esp32c2_chips}}): |
- | < | + | < |
- | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**GPIO**^**Flash (MB)**^**PSRAM (MB)**^**Antenna**^**Development Board**^ | + | |
- | | {{ : | + | |
- | |ESP8684-MINI-1U| ESP8684H2 \\ ESP8684H4|13.2×12.5×2.4|53| 14 | 1, 2, 4|N/A|IPEX antenna connector|ESP8684-DevKitM-1| | + | |
- | |ESP8684-WROOM-01C| ESP8684H2 \\ ESP8684H4|24×16×3.1| | + | |
- | |ESP8684-WROOM-02C| ESP8684H2 \\ ESP8684H4|18x20x3.2| 18 | 14 |2, 4|N/A|PCB antenna|N/ | + | |
- | |ESP8684-WROOM-02UC| ESP8684H2 \\ ESP8684H4|18x20x3.2|18 | 14 |2, 4|N/A|IPEX antenna connector|ESP8684-DevKitC-02| | + | |
- | |ESP8684-WROOM-03| ESP8684H2 \\ ESP8684H4|15×17.3×2.8|11| 8 | 2, 4|N/A|PCB antenna|N/ | + | |
- | |ESP8684-WROOM-04C| ESP8684H2 \\ ESP8684H4|24×16×3.1|17| 13 | 2, 4|N/A|PCB antenna|N/ | + | |
- | |ESP8684-WROOM-05| ESP8684H2 \\ ESP8684H4|15×17.3×2.8|7| 5 | 2, 4|N/A|PCB antenna|N/ | + | |
- | |ESP8684-WROOM-06C| ESP8684H2 \\ ESP8684H4|15.8×20.3×2.7|21| 14 or 5 | 2, 4|N/A|PCB antenna|N/ | + | |
- | |ESP8684-WROOM-07| ESP8684H2 \\ ESP8684H4|8.5x12.7x1.9|6| 3 | 2, 4|N/ | + | |
- | \\ \\ | + | |
< | < | ||
+ | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**GPIO**^**Flash (MB)**^**PSRAM (MB)**^**Antenna type**^**Development Board**^ | ||
+ | | {{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | |{{ : | ||
+ | | ||
+ | - **Note** 1: When surface mounted, the module has 14 available GPIOs; when vertically soldered, the module has 5 available GPIOs. \\ | ||
</ | </ | ||
- | ===ESP32-C3 General Information=== | + | ===== ESP32-C3 ===== |
+ | |||
+ | ==ESP32-C3 General Information== | ||
- | The ESP32-C3 family is a series of microcontrollers developed by Espressif Systems. It's based on the RISC-V architecture and is designed to offer low-power and cost-effective solutions for various IoT (Internet of Things) applications. These chips integrate | + | The ESP32-C3 family is a series of microcontrollers developed by Espressif Systems. It's based on the RISC-V architecture and is designed to offer low-power and cost-effective solutions for various IoT (Internet of Things) applications. These chips integrate |
The ESP32-C3 microcontrollers come with several distinctive features: | The ESP32-C3 microcontrollers come with several distinctive features: | ||
- | * RISC-V Core: One of the notable aspects of the ESP32-C3 family is the use of the RISC-V instruction set architecture, | + | * RISC-V Core: One of the notable aspects of the ESP32-C3 family is the use of the RISC-V instruction set architecture, |
- | * Wi-Fi Connectivity: | + | * WiFi Connectivity: |
- | * Low Power Consumption: | + | * Low Power Consumption: |
- | * Rich Peripheral Interface Support: The microcontrollers | + | * Rich Peripheral Interface Support: The microcontrollers |
* Security Features: The ESP32-C3 family includes various security features like secure boot, flash encryption, secure storage, and cryptographic accelerators. These elements contribute to the overall security of the devices developed using these microcontrollers. | * Security Features: The ESP32-C3 family includes various security features like secure boot, flash encryption, secure storage, and cryptographic accelerators. These elements contribute to the overall security of the devices developed using these microcontrollers. | ||
- | * Compact Form Factor: The ESP32-C3 family is designed in a compact form factor, which is advantageous for applications where space is limited or miniaturization is a concern. | + | * Compact Form Factor: The ESP32-C3 family is designed in a compact form factor, which is advantageous for applications where limited |
* Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | * Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | ||
- | For now the ESP32-C3 family includes the following chips in mass production (Table {{ref> | + | For now the ESP32-C3 family includes the following chips in mass production (table {{ref> |
<table esp32c3_chips> | <table esp32c3_chips> | ||
< | < | ||
- | ^**SoC**^**Variants**^**Core**^**Dimensions (mm)**^**Pins**^**RAM (KiB)**^**Flash (MiB)**^**PSRAM (MiB)**^ | + | ^**SoC**^**Variants**^**Core**^**Dimensions (mm)**^**Pins**^**RAM (kB)**^**Flash (MB)**^**PSRAM (MB)**^ |
- | |ESP32-C3(Figure | + | |ESP32-C3(figure |
- | |ESP8686(Figure | + | |ESP8686(figure |
- | |ESP8685(Figure | + | |ESP8685(figure |
\\ | \\ | ||
</ | </ | ||
Line 115: | Line 122: | ||
<figure esp32_c3> | <figure esp32_c3> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp8686> | <figure esp8686> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp8685> | <figure esp8685> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
== ESP32-C3 Architecture Overview == | == ESP32-C3 Architecture Overview == | ||
- | (Figure {{ref> | + | Figure {{ref> |
**Processors** | **Processors** | ||
Line 144: | Line 151: | ||
**Memory: Internal memory** | **Memory: Internal memory** | ||
- | * **Embedded flash** | + | * **Embedded flash** |
- | * **ROM:** 384 KiB (for booting and core functions). | + | * **ROM:** 384 kB (for booting and core functions). |
- | * **SRAM:** 400 KiB (16KiB for cache). | + | * **SRAM:** 400 kB (16kB for cache). |
- | * **RTC fast SRAM:** 8 KiB | + | * **RTC fast SRAM:** 8 kB |
* ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID | * ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID | ||
Line 159: | Line 166: | ||
* 3 × SPI (Serial Peripheral Interface), | * 3 × SPI (Serial Peripheral Interface), | ||
* 1 × I²S (Integrated Inter-IC Sound), | * 1 × I²S (Integrated Inter-IC Sound), | ||
- | * LED PWM up to 6 channels. | + | * LED PWM up to 6 channels, |
- | * Internal temperature sensor. | + | * Internal temperature sensor, |
- | * USB Serial/JTAG controller | + | * USB Serial/JTAG controller. |
**Security** | **Security** | ||
- | * Secure boot. | + | * Secure boot, |
- | * Flash encryption. | + | * Flash encryption, |
- | * 4096-bit OTP, up to 1792-bit for customers. | + | * 4096-bit OTP, up to 1792-bit for customers, |
* Cryptographic hardware acceleration: | * Cryptographic hardware acceleration: | ||
* AES-128/ | * AES-128/ | ||
Line 172: | Line 179: | ||
* RSA accelerator, | * RSA accelerator, | ||
* random number generator (RNG), | * random number generator (RNG), | ||
- | * digital signature | + | * digital signature. |
<figure esp32c3_functions> | <figure esp32c3_functions> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
==ESP32-C3 Modules== | ==ESP32-C3 Modules== | ||
- | Espressif also produces modules that are more integrative and more convenient for use by amateurs and developers. The following modules are currently available: | + | Espressif also produces modules that are more integrative and more convenient for amateurs and developers |
- | * ESP32-C3-Mini-1/ | + | * ESP32-C3-Mini-1/ |
- | * ESP32-C3-WROOM-02/ | + | * ESP32-C3-WROOM-02/ |
| | ||
<figure esp32_c3_mini1> | <figure esp32_c3_mini1> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
| | ||
<figure esp32_c3_wroom> | <figure esp32_c3_wroom> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
Line 197: | Line 204: | ||
==ESP32-C3 Development Kits== | ==ESP32-C3 Development Kits== | ||
- | Development kits are the most convenient for quick application or to check the capabilities of processors. | + | Development kits are the most convenient for quick application or to check the capabilities of processors. Espressif |
- | * Espressif - ESP32-C3-DevkitM-1((https:// | + | * Espressif - ESP32-C3-DevkitM-1((https:// |
- | * Espressif - ESP32-C3-DevkitC-02((https:// | + | * Espressif - ESP32-C3-DevkitC-02((https:// |
- | * Espressif - ESP32-C3-LCDKit ((https:// | + | * Espressif - ESP32-C3-LCDKit ((https:// |
- | * Adafruit - QT Py ESP32-C3 WiFi Dev Board with STEMMA QT((https:// | + | * Adafruit - QT Py ESP32-C3 WiFi Dev Board with STEMMA QT((https:// |
- | * Seeed Studio - XIAO ESP32C3 ((https:// | + | * Seeed Studio - XIAO ESP32C3 ((https:// |
- | * M5stack - M5Stamp-C3 ((https:// | + | * M5stack - M5Stamp-C3 ((https:// |
<figure esp32_c3_devkitm> | <figure esp32_c3_devkitm> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_c3_devkitc> | <figure esp32_c3_devkitc> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_c3_devkitlcd> | <figure esp32_c3_devkitlcd> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_c3_adafruit> | <figure esp32_c3_adafruit> | ||
- | {{ : | + | {{ : |
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_xiao> | <figure esp32_xiao> | ||
- | {{ : | + | {{ : |
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
<figure esp32_stampc3> | <figure esp32_stampc3> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
< | < | ||
== ESP32-C3 chip comparison == | == ESP32-C3 chip comparison == | ||
- | The Esp32-C3 as a more modern one, can successfully replace the oldest family of ESP8266 chips, so table {{ref> | + | The Esp32-C3 as a more modern one, can successfully replace the oldest family of ESP8266 chips, so table {{ref> |
<table esp32c3> | <table esp32c3> | ||
+ | < | ||
\\ | \\ | ||
^**Feature**^**ESP8266**^**ESP32-C3 Series**^ | ^**Feature**^**ESP8266**^**ESP32-C3 Series**^ | ||
Line 252: | Line 260: | ||
|ROM|384 KB |384 KB for booting and core functions| | |ROM|384 KB |384 KB for booting and core functions| | ||
|Embedded flash|✖️|4 MB or none, depending on variants| | |Embedded flash|✖️|4 MB or none, depending on variants| | ||
- | |RTC memory|768B|8KiB| | + | |RTC memory|768B|8kB| |
- | |Cache |32KB instruction|16KiB| | + | |Cache |32KB instruction|16kB| |
|PMU|✔️|✔️| | |PMU|✔️|✔️| | ||
|**Peripherals**| | |**Peripherals**| | ||
Line 297: | Line 305: | ||
|Size|QFN32 5*5|QFN32 5*5| | |Size|QFN32 5*5|QFN32 5*5| | ||
\\ | \\ | ||
- | < | ||
</ | </ | ||
- | ===ESP32-C6 General Information=== | + | ===== ESP32-C6 ===== |
- | ESP32-C6 is Espressif’s first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (Low Energy) and the 802.15.4 protocol. It is based a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, and also has a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. It has a 320KB ROM, a 512KB SRAM, and works with external flash. The ESP32-C6, with its support for Wi-Fi 6 and Bluetooth 5.3, can be a potential candidate for devices seeking to integrate into the Matter standard. Matter intends to create a universal standard for smart home devices to ensure interoperability and ease of use across different brands and ecosystems. Devices equipped with the ESP32-C6, can potentially comply with the Matter standard to ensure compatibility with other Matter-certified devices | + | |
+ | ==ESP32-C6 General Information== | ||
+ | ESP32-C6 is Espressif's first WiFi 6 SoC integrating 2.4 GHz WiFi 6, Bluetooth 5.3 (Low Energy) and the 802.15.4 protocol. It is based on a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, and also has a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. It has a 320KB ROM, a 512KB SRAM and works with external flash. The ESP32-C6, with its support for WiFi 6 and Bluetooth 5.3, can be a potential candidate for devices seeking to integrate into the Matter standard. Matter intends to create a universal standard for smart home devices to ensure interoperability and ease of use across different brands and ecosystems. Devices equipped with the ESP32-C6 can potentially comply with the Matter standard to ensure compatibility with other Matter-certified devices. They can be used to develop various other Matter-ecosystem solutions, such as Matter Gateways, Thread Border Routers or Zigbee Matter Bridges. However, adherence to the Matter standard involves hardware and software considerations, | ||
== ESP32-C6 Architecture Overview == | == ESP32-C6 Architecture Overview == | ||
- | (Figure {{ref> | + | Figure {{ref> |
**Processors** | **Processors** | ||
* **Main processor: | * **Main processor: | ||
- | * **Cores**: 1 | + | * **Cores**: 1, |
- | * External main crystal clock | + | * External main crystal clock, |
- | * External 32 kHz crystal oscillator for RTC or internal RC | + | * External 32 kHz crystal oscillator for RTC or internal RC. |
* **Low-power processor: | * **Low-power processor: | ||
- | * **Cores**: 1 | + | * **Cores**: 1, |
- | * External main crystal clock | + | * External main crystal clock, |
- | * External 32 kHz crystal oscillator for RTC or internal RC | + | * External 32 kHz crystal oscillator for RTC or internal RC. |
**Wireless connectivity** | **Wireless connectivity** | ||
- | * **WiFi: | + | * **WiFi: |
- | * ** WiFI: | + | * ** WiFI: |
- | * **Bluetooth: | + | * **Bluetooth: |
- | * **IEEE 802.15.4-2015: | + | * **IEEE 802.15.4-2015: |
**Memory: Internal memory** | **Memory: Internal memory** | ||
- | * **Embedded flash** | + | * **Embedded flash** |
- | * **ROM:** 320 KiB (for booting and core functions). | + | * **ROM:** 320 kB (booting and core functions), |
- | * **HP SRAM:** 510 KiB | + | * **HP SRAM:** 510 kB, |
- | * ** LP SRAM:** 16 KiB | + | * ** LP SRAM:** 16 kB, |
- | * **RTC fast SRAM:** 8 KiB | + | * **RTC fast SRAM:** 8 kB, |
- | * ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID | + | * ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID. |
**Peripheral Input/ | **Peripheral Input/ | ||
- | * 30xGPIO (QFN40) or 22xGPIO (QFN32) | + | * 30xGPIO (QFN40) or 22xGPIO (QFN32), |
* General DMA controller (GDMA), with 3 transmit channels and 3 receive channels, | * General DMA controller (GDMA), with 3 transmit channels and 3 receive channels, | ||
* 1 × I²C (Inter-Integrated Circuit), | * 1 × I²C (Inter-Integrated Circuit), | ||
Line 340: | Line 349: | ||
* 1 × SPI (Serial Peripheral Interface universal ), | * 1 × SPI (Serial Peripheral Interface universal ), | ||
* 1 × I²S (Integrated Inter-IC Sound), | * 1 × I²S (Integrated Inter-IC Sound), | ||
- | * 1 × SDIO 2.0 slave controller | + | * 1 × SDIO 2.0 slave controller, |
- | * 1 × Motor Control PWM (MCPWM) | + | * 1 × Motor Control PWM (MCPWM), |
- | * LED PWM up to 6 channels. | + | * LED PWM up to 6 channels, |
- | * 1 x USB Serial/JTAG controller | + | * 1 x USB Serial/JTAG controller, |
- | * 1 x Remote control peripheral (TX/RX) | + | * 1 x Remote control peripheral (TX/RX), |
- | * 1 x Parallel IO interface (PARLIO) | + | * 1 x Parallel IO interface (PARLIO), |
* 1 x 12-bit SAR ADCs (analog-to-digital converter) up to 7 channels, | * 1 x 12-bit SAR ADCs (analog-to-digital converter) up to 7 channels, | ||
- | * 1 x temperature sensor | + | * 1 x temperature sensor. |
**Security** | **Security** | ||
- | * Secure boot. | + | * Secure boot, |
- | * Flash encryption. | + | * Flash encryption, |
- | * External Memory Encryption and Decryption (XTS_AES) | + | * External Memory Encryption and Decryption (XTS_AES), |
- | * 4096-bit OTP, up to 1792-bit for customers. | + | * 4096-bit OTP, up to 1792-bit for customers, |
- | * Trusted execution environment (TEE) controller and access permission management (APM) | + | * Trusted execution environment (TEE) controller and access permission management (APM), |
* Cryptographic hardware acceleration: | * Cryptographic hardware acceleration: | ||
* AES-128/ | * AES-128/ | ||
- | * ECC | + | * ECC, |
* SHA accelerator, | * SHA accelerator, | ||
* RSA accelerator, | * RSA accelerator, | ||
- | * HASH (FIPS PUB 180-4) | + | * HASH (FIPS PUB 180-4), |
* random number generator (RNG), | * random number generator (RNG), | ||
- | * digital signature | + | * digital signature. |
<figure esp32c6_functions> | <figure esp32c6_functions> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
==ESP32-C6 Modules== | ==ESP32-C6 Modules== | ||
- | The following modules are currently available (Table {{ref> | + | The following modules are currently available (table {{ref> |
<table esp32c6_modules> | <table esp32c6_modules> | ||
- | |||
- | ^**Module**^**Chip embedded**^**Dimensions (mm)**^**Pins**^**Development board**^ | ||
- | |ESP32-C6-Mini-1/ | ||
- | |ESP32-C6-WROOM-02/ | ||
< | < | ||
+ | ^**Module**^**Chip embedded**^**Dimensions (mm)**^**Pins**^**Development board**^ | ||
+ | |ESP32-C6-Mini-1/ | ||
+ | |ESP32-C6-WROOM-02/ | ||
+ | |||
</ | </ | ||
<figure esp32_c6_mini1> | <figure esp32_c6_mini1> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
| | ||
<figure esp32_c6_wroom> | <figure esp32_c6_wroom> | ||
- | {{ : | + | {{ : |
- | < | + | < |
</ | </ | ||
==ESP32-C6 Development Boards== | ==ESP32-C6 Development Boards== | ||
There are not many prototype kits with ESP32-C6 SOCs on the market yet. Two sets released by the manufacturer deserve special attention. They are both entry-level development boards: | There are not many prototype kits with ESP32-C6 SOCs on the market yet. Two sets released by the manufacturer deserve special attention. They are both entry-level development boards: | ||
- | * Espressif - ESP32-C6-DevkitM-1 ((https:// | + | * Espressif - ESP32-C6-DevkitM-1 ((https:// |
- | * Espressif - ESP32-C6-DevkitC-1((https:// | + | * Espressif - ESP32-C6-DevkitC-1((https:// |
<figure esp32_c6_devkitm> | <figure esp32_c6_devkitm> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
| | ||
<figure esp32_c6_devkitc> | <figure esp32_c6_devkitc> | ||
- | {{ : | + | {{ : |
< | < | ||
</ | </ | ||
- | They allow you to test all functions of the processor including | + | They allow you to test all processor |
- | <note important> | + | <note important> |
</ | </ | ||