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en:iot-open:embeddedcommunicationprotocols2:spi [2023/09/06 08:44] – ekontoturboen:iot-open:embeddedcommunicationprotocols2:spi [2024/05/27 10:16] (current) – [QSPI] ktokarz
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-===== SPI ===== +====== SPI ====== 
-One of the most popular interfaces to connect different external devices is SPI (Serial Peripheral Interface). It is a synchronous serial interface and protocol that can transmit data with speeds up to 20 Mbps. SPI is used to communicate microcontrollers with one or more peripheral devices over short distances – usually internally in the device. High transmission speed enables SPI to be suitable even for sending animated video data to colourful displays. In SPI connection, there is always one master device, in most cases the microcontroller (μC) that controls the transmission, and one or more slave devices – peripherals. To communicate, SPI uses three lines common to all connected devices and one enabling line for every slave element. +{{:en:iot-open:czapka_b.png?50| General audience classification icon }}{{:en:iot-open:czapka_e.png?50| General audience classification icon }}\\ 
-<table Ref.Tab.1>+One of the most popular interfaces to connect different external devices is SPI (Serial Peripheral Interface). It is a synchronous serial interface and protocol that can transmit data with speeds up to 20 Mbps. SPI is used to communicate microcontrollers with one or more peripheral devices over short distances – usually internally in the device. High transmission speed enables SPI to be suitable even for sending animated video data to colourful displays. In SPI connection, there is always one master device, in most cases the microcontroller (μC) that controls the transmission, and one or more slave devices – peripherals. To communicate, SPI uses three lines common to all connected devices and one enabling line for every slave element (table {{ref>RefTabSPI1}}). 
 +<table RefTabSPI1>
 <caption>SPI Lines</caption> <caption>SPI Lines</caption>
-^ <fs xx-small>Line</fs> ^ <fs xx-small>Description</fs> ^ <fs xx-small>Direction</fs> ^ +^ Line ^ Description ^ Direction ^ 
-| <fs xx-small>MISO</fs> | <fs xx-small>Master In Slave Out</fs> | <fs xx-small>peripheral -> μC</fs> | +| MISO | Master In Slave Out | peripheral -> μC | 
-| <fs xx-small>MOSI</fs> | <fs xx-small>Master Out Slave In</fs> | <fs xx-small>μC -> peripheral</fs> | +| MOSI | Master Out Slave In | μC -> peripheral | 
-| <fs xx-small>SCK</fs> | <fs xx-small>Serial Clock</fs> | <fs xx-small>μC -> peripheral</fs> | +| SCK | Serial Clock | μC -> peripheral | 
-| <fs xx-small>SS</fs> | <fs xx-small>Slave Select</fs> | <fs xx-small>μC -> peripheral</fs> |+| SS | Slave Select | μC -> peripheral |
 </table>    </table>   
-The MISO line is intended to send bits from slave to master, the MOSI wire transmits data from master to slave, and the SCK line sends clock pulses that synchronize data transmission. The master device always generates the clock signal. +The MISO line is intended to send bits from slave to master, the MOSI wire transmits data from master to slave, and the SCK line sends clock pulses that synchronise data transmission. The master device always generates the clock signal. 
-Every SPI-compatible device has the SS (Slave Select) input that enables communication in this specific device. Master is responsible for generating this enable signal – separately for every slave in the system. +Every SPI-compatible device has the SS (Slave Select) input that enables communication in this specific device. Master is responsible for generating this enable signal – separately for every slave in the system, as present in figure {{ref>RefSPIPic1}}. 
-<figure Ref.Pic.1> +<figure RefSPIPic1> 
-{{ :en:iot-open:embeddedcommunicationprotocols2:spi_diagram.png?nolink&500 | SPI connections }} +{{ :en:iot-open:embeddedcommunicationprotocols2:spi_diagram.png?500 | Sample SPI connections }} 
-<caption>Sample SPI connection.</caption>+<caption>Sample SPI connection</caption>
 </figure>   </figure>  
  
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   * communication interfaces (e.g. Ethernet, WiFi),    * communication interfaces (e.g. Ethernet, WiFi), 
   * and many others.   * and many others.
-Due to different hardware implementations, there are four SPI protocol operation modes. The mode used in the master must fit the mode implemented in the slave device. +Due to different hardware implementations, there are four SPI protocol operation modes (table {{ref>RefSPITab2}}). The mode used in the master must fit the mode implemented in the slave device. 
-<table Ref.Tab.2>+<table RefSPITab2>
 <caption>SPI Modes</caption> <caption>SPI Modes</caption>
-^ <fs xx-small>Mode</fs> ^ <fs xx-small>Clock polarity</fs> ^ <fs xx-small>Clock phase</fs> ^ <fs xx-small>Idle state</fs> ^ <fs xx-small>Active state</fs> ^ <fs xx-small>Output edge</fs> ^ <fs xx-small>Data capture</fs> ^ +^ Mode ^ Clock polarity ^ Clock phase ^ Idle state ^ Active state ^ Output edge ^ Data capture ^ 
-| <fs xx-small>mode 0</fs> | <fs xx-small>0</fs> | <fs xx-small>0</fs> | <fs xx-small>0</fs> | <fs xx-small>1</fs> | <fs xx-small>falling</fs> | <fs xx-small>rising</fs> | +| mode 0 | 0 | 0 | 0 | 1 | falling | rising | 
-| <fs xx-small>mode 1</fs> | <fs xx-small>0</fs> | <fs xx-small>1</fs> | <fs xx-small>0</fs> | <fs xx-small>1</fs> | <fs xx-small>rising</fs> | <fs xx-small>falling</fs> | +| mode 1 | 0 | 1 | 0 | 1 | rising | falling | 
-| <fs xx-small>mode 2</fs> | <fs xx-small>1</fs> | <fs xx-small>0</fs> | <fs xx-small>1</fs> | <fs xx-small>0</fs> | <fs xx-small>rising</fs> | <fs xx-small>falling</fs> | +| mode 2 | 1 | 0 | 1 | 0 | rising | falling | 
-| <fs xx-small>mode 3</fs> | <fs xx-small>1</fs> | <fs xx-small>1</fs> | <fs xx-small>1</fs> | <fs xx-small>0</fs> | <fs xx-small>falling</fs> | <fs xx-small>rising</fs> |+| mode 3 | 1 | 1 | 1 | 0 | falling | rising |
 </table> </table>
  
-It results in different timings of the clock signal concerning the data sent. Clock polarity = 0 means that the idle state of the SCK is 0, so every data bit is synchronised with the pulse of logic 1. Clock polarity = 1 reverses these states. Output edge (rising/falling) says at which edge of active SCK signal sender puts a bit on the data line. The data capture edge says at what edge of SCK signal data should be captured by the receiver.+It results in different timings of the clock signal concerning the data sent (figure {{ref>RefSPIPic2}}). Clock polarity = 0 means that the idle state of the SCK is 0, so every data bit is synchronised with the pulse of logic 1. Clock polarity = 1 reverses these states. Output edge (rising/falling) says at which edge of active SCK signal sender puts a bit on the data line. The data capture edge says at what edge of SCK signal data should be captured by the receiver.
  
-<figure Ref.Pic.2> +<figure RefSPIPic2> 
-{{ :en:iot-open:embeddedcommunicationprotocols2:spi_timing.png?nolink&500 | SPI timing }} +{{ :en:iot-open:embeddedcommunicationprotocols2:spi_timing.png?500 | Sample SPI timing }} 
-<caption>Sample SPI timing.</caption>+<caption>Sample SPI timing</caption>
 </figure>   </figure>  
  
 ===== QSPI ===== ===== QSPI =====
-Even if a 20MHz frequency ensures good transmission speed, it can be too slow for some use. Some modern microcontrollers use external flash memory for program storage and execute programs from internal SRAM memory, downloading executable code in chunks as required. This requires a higher data rate to avoid stalls in program execution. A QSPI (Quad-SPI) link was developed to achieve higher transmission speed. It has four bidirectional data lines instead of two unidirectional to increase speed four times. Additionally, it supports higher clock frequency, increasing speed even higher, currently more than 100MBps. Operation of QSPI requires a special protocol with a set of commands, so hardware implementation is much more complex than the original SPI.+Even if a 20MHz frequency ensures good transmission speed, it can be too slow for some use. Some modern microcontrollers use external flash memory for program storage and execute programs from internal SRAM memory, downloading executable code in chunks as required. This requires a higher data rate to avoid stalls in program execution. A QSPI (Quad-SPI) link was developed to achieve higher transmission speed. It has four bidirectional data lines instead of two unidirectional to increase speed four times (figure {{ref>RefSPIPic3}}). Additionally, it supports higher clock frequency, increasing speed even higher, currently more than 100MBps. Operation of QSPI requires a special protocol with a set of commands, so hardware implementation is much more complex than the original SPI.
  
-<figure Ref.Pic.3> +<figure RefSPIPic3> 
-{{ :en:iot-open:embeddedcommunicationprotocols2:qspi_diagram.png?nolink&500 | QSPI connections }} +{{ :en:iot-open:embeddedcommunicationprotocols2:qspi_diagram.png?500 | Sample QSPI connections }} 
-<caption>Sample QSPI connection.</caption>+<caption>Sample QSPI connection</caption>
 </figure>   </figure>  
  
en/iot-open/embeddedcommunicationprotocols2/spi.1693989892.txt.gz · Last modified: 2023/09/06 05:44 (external edit)
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