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en:multiasm:papc:chapter_6_3 [2025/05/09 14:27] – [ZMM registers] ktokarzen:multiasm:papc:chapter_6_3 [2025/05/09 14:29] (current) – [XMM registers] ktokarz
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 </figure> </figure>
  
-To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented {{ref>mxcsrreg}}. It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.+To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.
  
 <figure mxcsrreg> <figure mxcsrreg>
en/multiasm/papc/chapter_6_3.1746800839.txt.gz · Last modified: 2025/05/09 14:27 by ktokarz
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