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| en:multiasm:papc:chapter_6_3 [2025/05/09 14:24] – [ZMM registers] ktokarz | en:multiasm:papc:chapter_6_3 [2025/05/09 14:29] (current) – [XMM registers] ktokarz |
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| </figure> | </figure> |
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| To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented {{ref>mxcsrreg}}. It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together. | To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together. |
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| <figure mxcsrreg> | <figure mxcsrreg> |
| <caption>512-bit ZMM registers</caption> | <caption>512-bit ZMM registers</caption> |
| </figure> | </figure> |
| | XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}} |
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| | <figure xyzmmregs> |
| | {{ :en:multiasm:cs:xyzmm_register.png?800 |Illustration of the relation between XMM, YMM and ZMM registers}} |
| | <caption>The relation between XMM, YMM and ZMM registers</caption> |
| | </figure> |
| Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors (figure {{ref>opmaskregs}}). They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions. | Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors (figure {{ref>opmaskregs}}). They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions. |
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| </figure> | </figure> |
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| <note> | |
| XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}} | |
| </note> | |
| <figure xyzmmregs> | |
| {{ :en:multiasm:cs:xyzmm_register.png?400 |Illustration of the relation between XMM, YMM and ZMM registers}} | |
| <caption>The relation between XMM, YMM and ZMM registers</caption> | |
| </figure> | |
| ===== Additional registers ===== | ===== Additional registers ===== |
| In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable. | In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable. |
| Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)). | Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)). |
