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--- en:multiasm:papc:chapter_6_3 [2025/05/09 11:07] – [YMM registers] ktokarz
+++ en:multiasm:papc:chapter_6_3 [2025/05/09 14:29] (current) – [XMM registers] ktokarz
@@ Line 144: / Line 144: @@
 {{ :en:multiasm:cs:xmm_registers.png?500 |Illustration of the 128-bit XMM registers}}
 <caption>128-bit XMM registers</caption>
+</figure>
+To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together.
+<figure mxcsrreg>
+{{ :en:multiasm:cs:mxcsr_register.png?500 |Illustration of the MXCSR SSE control register}}
+<caption>MXCSR control register for SSE unit</caption>
 </figure>
 ===== YMM registers =====
-The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, the number of these registers was increased to 16 (figure {{ref>ymmregs}}.
+The YMM registers are the 256-bit extension to the XMM registers. They are introduced to implement the AVX set of instructions. Additionally, in 64-bit processors, the number of available YMM registers was increased to 16 (figure {{ref>ymmregs}}).
 <figure ymmregs>
-{{ :en:multiasm:cs:ymm_registers.png?500 |Illustration of the 256-bit YMM registers}}
+{{ :en:multiasm:cs:ymm_registers.png?600 |Illustration of the 256-bit YMM registers}}
 <caption>256-bit YMM registers</caption>
 </figure>
 ===== ZMM registers =====
--bit registers + opmask registers
+ZMM registers are the further extension of XMM registers to 512 bits. In 64-bit machines, 32 of such registers are available (figure {{ref>zmmregs}}).
+<figure zmmregs>
+{{ :en:multiasm:cs:zmm_registers.png?800 |Illustration of the 512-bit ZMM registers}}
+<caption>512-bit ZMM registers</caption>
+</figure>
+XMM are the physical lower halves of YMM, which are the lower halves of ZMM. Anything written to the XMM register appears in part of the YMM and ZMM registers as presented in figure {{ref>xyzmmregs}}
+<figure xyzmmregs>
+{{ :en:multiasm:cs:xyzmm_register.png?800 |Illustration of the relation between XMM, YMM and ZMM registers}}
+<caption>The relation between XMM, YMM and ZMM registers</caption>
+</figure>
+Together with AVX extension and ZMM registers, eight 16-bit opmask registers were introduced to x64 processors (figure {{ref>opmaskregs}}). They can be used, e.g. to provide conditional execution or mask several elements of vectors in AVX instructions.
+<figure opmaskregs>
+{{ :en:multiasm:cs:opmask_registers.png?400 |Illustration of the opmask registers}}
+<caption>Opmask registers</caption>
+</figure>
 ===== Additional registers =====
 In the x64 architecture, there are additional registers used for control purposes. The CR0, CR2, CR3, CR4, and CR8 registers are used for controlling the operating mode of the processor, virtual and protected memory mechanisms and paging. The debug registers, named DR0 through DR7, control the debugging of the processor’s operations and software. Memory type range registers MTRR can be used to map the address space used for the memory-mapped I/O as non-cacheable.
 Different processors have different sets of model-specific registers, MSR. There are also machine check registers MCR. They are used to control and report on processor performance, detect and report hardware errors. Mostly, the described registers are not accessible to an application program and are controlled by the operating system, so they will not be described in this book. For more details, please refer to Intel documentation ((https://www.intel.com/content/www/us/en/content-details/851056/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-1-basic-architecture.html?wapkw=253665)).

en/multiasm/papc/chapter_6_3.1746788844.txt.gz · Last modified: 2025/05/09 11:07 by ktokarz