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--- en:multiasm:cs:chapter_3_9 [2025/12/05 11:31] – [Superscalar] ktokarz
+++ en:multiasm:cs:chapter_3_9 [2025/12/05 11:37] (current) – [Hyperthreading] ktokarz
@@ Line 41: / Line 41: @@
 </table>
-<note info>
-The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance, e.g. out-of-order execution and register renaming. They are performed automatically by the processor, and the assembler programmer does not influence their behaviour.
-</note>
@@ Line 55: / Line 53: @@
 For each physical core, the operating system defines two logical processor cores and shares the load between them when possible. The hyperthreading technology uses a superscalar architecture to increase the number of instructions that operate in parallel in the pipeline on separate data. With Hyper-Threading, one physical core appears to the operating system as two separate processors. The logical processors share the execution resources, including the execution engine, caches, and system bus interface. Only the elements that store the architectural state of the processor are duplicated, including essential registers for code execution.
+<note info>
+The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance, e.g. out-of-order execution and register renaming. They are performed automatically by the processor, and the assembler programmer does not influence their behaviour.
+</note>

en/multiasm/cs/chapter_3_9.1764934286.txt.gz · Last modified: 2025/12/05 11:31 by ktokarz