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en:multiasm:cs:chapter_3_9 [2025/12/05 11:03] – [Pipeline] ktokarzen:multiasm:cs:chapter_3_9 [2025/12/05 11:37] (current) – [Hyperthreading] ktokarz
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 ===== Superscalar ===== ===== Superscalar =====
-The superscalar processor increases the speed of program execution because it can execute more than one instruction during a clock cycle. It is realised by simultaneously dispatching instructions to different execution units on the processor. The superscalar processor doesn't implement two or more independent pipelines, rather decoded instructions are sent for further processing to the chosen execution unit as shown in Fig. {{ref>superscalar}}.+The superscalar processor increases the speed of program execution because it can execute more than a single instruction during a clock cycle. It is realised by simultaneously dispatching instructions to different execution units on the processor. The superscalar processor can, but doesn'have to, implement two or more independent pipelines. Rather, decoded instructions are sent for further processing to the chosen execution unit as shown in Fig. {{ref>superscalar}}.
  
 <figure superscalar> <figure superscalar>
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 </figure> </figure>
  
-In the x86 family first processor with two paths of execution was Pentium with U and V pipelines. Modern x64 processors like i7 implement six execution units. Not all execution units have the same functionality, for example, In the i7 processor, every execution unit has different possibilities, as presented in table {{ref>executionunits}}.+In the x86 family first processor with two paths of execution was the Pentium with two execution units called U and V. Modern x64 processors like i7 implement six execution units. Not all execution units have the same functionality. For example, in the i7 processor, every execution unit has different possibilities, as presented in table {{ref>executionunits}}.
  
 <table executionunits> <table executionunits>
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 </table> </table>
  
-<note info> +
-The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance e.g. out-of-order execution, and register renaming. They are performed automatically by the processor and the assembler programmer does not influence their behaviour. +
-</note>+
  
  
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 ===== Hyperthreading ===== ===== Hyperthreading =====
-Hyper-Threading Technology is an Intel approach to simultaneous multithreading technology which allows the operating system to execute more than one thread on a single physical core.  +Hyper-Threading Technology is an Intel approach to simultaneous multithreading technologywhich allows the operating system to execute more than one thread on a single physical core.  
-For each physical core, the operating system defines two logical processor cores and shares the load between them when possible. The hyperthreading technology uses a superscalar architecture to increase the number of instructions that operate in parallel in the pipeline on separate data. With Hyper-Threading, one physical core appears to the operating system as two separate processors. The logical processors share the execution resources including the execution engine, caches, and system bus interface. Only the elements that store the architectural state of the processor are duplicated including essential registers for the code execution. +For each physical core, the operating system defines two logical processor cores and shares the load between them when possible. The hyperthreading technology uses a superscalar architecture to increase the number of instructions that operate in parallel in the pipeline on separate data. With Hyper-Threading, one physical core appears to the operating system as two separate processors. The logical processors share the execution resourcesincluding the execution engine, caches, and system bus interface. Only the elements that store the architectural state of the processor are duplicatedincluding essential registers for code execution.
  
 +<note info>
 +The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance, e.g. out-of-order execution and register renaming. They are performed automatically by the processor, and the assembler programmer does not influence their behaviour.
 +</note>
en/multiasm/cs/chapter_3_9.1764932590.txt.gz · Last modified: 2025/12/05 11:03 by ktokarz
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