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As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three stages description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps. The five stages version adds another final step for writing the result back and sometimes reverses the steps of data read and execution.
It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor's architecture, implementation and complexity. Considering the five-stage model we can describe the general model of instruction execution:
As you can see from this description execution of a single instruction requires many activities which must be performed by the processor. We can notice that each stage, or even sub-stage can be done by a separate logic unit. This feature is used by designers of modern processors to create the pipeline. The pipeline is the set of logic units which execute many instructions at the same time - each of them at a different stage of execution. If the instructions are coming in an undisrupted stream the pipeline makes it possible to execute the program faster than by a non-pipelined processor.
Instruction encoding constant size