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| en:multiasm:cs:chapter_3_8 [2025/01/06 18:26] – ktokarz | en:multiasm:cs:chapter_3_8 [2025/12/05 09:59] (current) – [Instruction Execution Process] ktokarz | ||
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| ===== Instruction Execution Process ====== | ===== Instruction Execution Process ====== | ||
| - | As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three stages | + | As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three-stage |
| - | It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor' | + | It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor' |
| - Fetching the instruction: | - Fetching the instruction: | ||
| - | * The processor addresses the instruction by sending the content of the IP register | + | * The processor addresses the instruction by sending the content of the IP register |
| - | * The processor reads the code of the instruction from program memory | + | * The processor reads the code of the instruction from program memory |
| * The processor stores the code of the instruction in the instruction register. | * The processor stores the code of the instruction in the instruction register. | ||
| * The processor prepares the IP (possibly increments) to point to the next instruction in a stream. | * The processor prepares the IP (possibly increments) to point to the next instruction in a stream. | ||
| - Instruction decoding: | - Instruction decoding: | ||
| - | * A simple instruction can be interpreted directly by instruction decoder logic. | + | * A simple instruction can be interpreted directly by the instruction decoder logic. |
| * More complex instructions are processed in some steps by microcodes. | * More complex instructions are processed in some steps by microcodes. | ||
| * Results are provided to the execution unit. | * Results are provided to the execution unit. | ||
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| - Instruction execution: | - Instruction execution: | ||
| * The execution unit performs actions as encoded in the instruction (simple or with microcode). | * The execution unit performs actions as encoded in the instruction (simple or with microcode). | ||
| - | * In modern processors there are more execution units, they can execute | + | * In modern processors, there are more execution units, |
| - Writing back the result: | - Writing back the result: | ||
| * The processor writes the result of calculations into the register or memory. | * The processor writes the result of calculations into the register or memory. | ||
| ===== Instruction encoding ===== | ===== Instruction encoding ===== | ||
| - | From the perspective of the processor, instructions are binary codes, unambiguously determining the activities that the processor is to perform. Instructions can be encoded using a fixed or variable number of bits. | + | From the perspective of the processor, instructions are binary codes, unambiguously determining the activities that the processor is to perform. Instructions can be encoded using a fixed or variable number of bits. |
| - | A fixed number of bits makes the construction of the instruction decoder simpler because the choice of some specific behaviour or function of the execution unit is encoded with the bits which are always at the same position in the instruction. On the opposite side, if the designer plans to expand the instruction set with new instructions in the future, there must be some spare bits in the instruction word reserved for future use. It makes the code of the program larger than required. Fixed lengths of instructions are often implemented in RISC machines. | + | A fixed number of bits makes the construction of the instruction decoder simpler because the choice of some specific behaviour or function of the execution unit is encoded with the bits, which are always at the same position in the instruction. On the opposite side, if the designer plans to expand the instruction set with new instructions in the future, there must be some spare bits in the instruction word reserved for future use. It makes the code of the program larger than required. Fixed lengths of instructions are often implemented in RISC machines. For example, in the ARM architecture, |
| - | A variable number of bits makes the instruction decoder more complex. Based on the content of the first part of the instruction (usually byte) it must be able to decide what is the length of the whole instruction. In such an approach, instructions can be as short as one byte, or much longer. An example of a processor with variable instruction length is 8086 and all further processors from the x86 and x64 families. Here the instructions, | + | A variable number of bits makes the instruction decoder more complex. Based on the content of the first part of the instruction (usually |
| - | Instruction encoding | + | <note info> |
| - | constant size | + | Although in the computer world information is very often encoded in bytes or multiples of bytes, there are processors with instructions encoded in other numbers of bits. Examples include PIC microcontrollers with an instruction length of 13 or 14 bits.</ |
