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--- en:multiasm:cs:chapter_3_8 [2025/01/06 16:32] – ktokarz
+++ en:multiasm:cs:chapter_3_8 [2025/12/05 09:59] (current) – [Instruction Execution Process] ktokarz
@@ Line 1: / Line 1: @@
 ===== Instruction Execution Process ======
-As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three stages description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps. The five stages version adds another final step for writing the result back and sometimes reverses the steps of data read and execution.
+As we already mentioned, instructions are executed by the processor in a few steps. You can find in the literature descriptions that there are three, four, or five stages of instruction execution. Everything depends on the level of detail one considers. The three-stage description says that there are fetch, decode and execute steps. The four-stage model says that there are fetch, decode, data read and execute steps. The five-stage version adds another final step for writing the result back and sometimes reverses the steps of data read and execution.
-It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor's architecture, implementation and complexity. Considering the five-stage model we can describe the general model of instruction execution:
+It is worth remembering that even a simple fetch step can be divided into a set of smaller actions which must be performed by the processor. The real execution of instructions depends on the processor's architecture, implementation and complexity. Considering the five-stage model, we can describe the general stages of instruction execution:
   - Fetching the instruction:
-    * The processor addresses the instruction by sending the content of the IP register by the address bus.
+    * The processor addresses the instruction by sending the content of the IP register on the address bus.
-    * The processor reads the code of the instruction from program memory by data bus.
+    * The processor reads the code of the instruction from program memory through the data bus.
     * The processor stores the code of the instruction in the instruction register.
     * The processor prepares the IP (possibly increments) to point to the next instruction in a stream.
   - Instruction decoding:
-    * A simple instruction can be interpreted directly by instruction decoder logic.
+    * A simple instruction can be interpreted directly by the instruction decoder logic.
     * More complex instructions are processed in some steps by microcodes.
     * Results are provided to the execution unit.
@@ Line 18: / Line 18: @@
   - Instruction execution:
     * The execution unit performs actions as encoded in the instruction (simple or with microcode).
-    * In modern processors there are more execution units, they can execute different instructions simultaneously.
+    * In modern processors, there are more execution units, and they can execute several instructions simultaneously.
   - Writing back the result:
     * The processor writes the result of calculations into the register or memory.
-As you can see from this description, executing a single instruction requires many actions that must be performed by the processor. We can see that each step, or even substep, can be performed by a separate logical unit. This feature has been used by designers of modern processors to create a processor in which instructions are executed in a pipeline. A pipeline is a collection of logical units that execute many instructions at the same time - each of them at a different stage of execution. If the instructions arrive in a continuous stream, the pipeline allows the program to execute faster than a processor that does not support the pipeline.
+===== Instruction encoding =====
+From the perspective of the processor, instructions are binary codes, unambiguously determining the activities that the processor is to perform. Instructions can be encoded using a fixed or variable number of bits.
+A fixed number of bits makes the construction of the instruction decoder simpler because the choice of some specific behaviour or function of the execution unit is encoded with the bits, which are always at the same position in the instruction. On the opposite side, if the designer plans to expand the instruction set with new instructions in the future, there must be some spare bits in the instruction word reserved for future use. It makes the code of the program larger than required. Fixed lengths of instructions are often implemented in RISC machines. For example, in the ARM architecture, instructions have 32 bits. In AVR, instructions are encoded using 16 bits.
-Instruction encoding
+A variable number of bits makes the instruction decoder more complex. Based on the content of the first part of the instruction (usually a byte), it must be able to decide what is the length of the whole instruction. In such an approach, instructions can be as short as one byte or much longer. An example of a processor with variable instruction length is the 8086 and all further processors from the x86 and x64 families. Here, the instructions, including all possible constant arguments, can have even 15 bytes.
-constant size
+<note info>
+Although in the computer world information is very often encoded in bytes or multiples of bytes, there are processors with instructions encoded in other numbers of bits. Examples include PIC microcontrollers with an instruction length of 13 or 14 bits.</note>

en/multiasm/cs/chapter_3_8.1736181176.txt.gz · Last modified: 2025/01/06 16:32 by ktokarz