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--- en:multiasm:cs:chapter_3_7 [2024/09/27 19:18] – created pczekalski
+++ en:multiasm:cs:chapter_3_7 [2025/12/04 13:42] (current) – [Separate I/O address space] ktokarz
@@ Line 1: / Line 1: @@
-====== Peripherals (do we go into details?) general description of generic device ======
+====== Peripherals ======
+Peripherals or peripheral devices, also known as Input-Output devices, enable the computer to remain in contact with the external environment or expand the computer's functionality. Peripheral devices enhance the computer's capability by making it possible to enter information into a computer for storage or processing and to deliver the processed data to a user, another computer, or a device controlled by the computer.
+Internal peripherals are connected directly to the address, data, and control buses of the computer. External peripherals can be connected to the computer via USB or a similar connection.
+<note info>
+The USB controller is also a peripheral device, so every external peripheral (e.g. mouse) is connected to the processor via an internal peripheral. In this book, we consider internal peripherals directly connected to the address, data, and control buses.
+</note>
+===== Types of peripherals =====
+There is a variety of peripherals which can be connected to the computer. The most commonly used are:
+  * parallel input/output ports
+  * serial communication ports
+  * timers/counters
+  * analogue to digital converters
+  * digital to analogue converters
+  * interrupt controllers
+  * DMA controllers
+  * displays
+  * keyboards
+  * sensors
+  * actuators
+===== Addressing of I/O devices =====
+From the assembler programmer's perspective, the peripheral device is represented as a set of registers available in the I/O address space. Registers of peripherals are used to control their behaviour, including mode of operation, parameters, configuration, speed of transmission, etc. Registers are also data exchange points where the processor can store data to be transmitted to the user or external computer, or read the data coming from the user or another system.
+The size of the I/O address space is usually smaller than the size of the program or data address space. The method of accessing peripherals depends on the design of the processor. We can find two methods of I/O addressing implementation: separate or memory-mapped I/O.
+===== Separate I/O address space =====
+A separate I/O address space is accessed independently of the program or data memory. In the processor, it is implemented with the use of separate control bus lines to read or write I/O devices. Separate control lines usually mean that the processor also implements different instructions to access memory and I/O devices. It also means that the chosen peripheral and byte in the memory can have the same address, and only the type of instruction used distinguishes the final destination of the address.
+Separate I/O address space is shown schematically in Fig {{ref>separateio}}. Reading the data from the memory is activated with the #MEMRD signal, writing with the #MEMWR signal. If the processor needs to read or write the register of the peripheral device, it uses #IORD or #IOWR lines, respectively.
+<note info>
+The "#" symbol before a signal name means that the active signal on the line is a LOW state while idle is a HIGH state.
+</note>
+<figure separateio>
+{{ :en:multiasm:cs:separate_io.png?600 |Separate I/O address space}}
+<caption>Separate I/O address space</caption>
+</figure>
+===== Memory-mapped I/O address space =====
+In this approach, the processor doesn't implement separate control signals to access the peripherals. It uses a #RD signal to read the data from and a #WR signal to write the data to a common address space. It also doesn't have different instructions to access registers in the I/O address space. Every such register is visible like any other memory location. It means that this is only the responsibility of the software to distinguish the I/O registers and data in the memory.
+Memory-mapped I/O address space is shown schematically in Fig {{ref>memorymappedio}}.
+<figure memorymappedio>
+{{ :en:multiasm:cs:memory_mapped_io.png?600 |Memory-mapped I/O address space}}
+<caption>Memory-mapped I/O address space</caption>
+</figure>

en/multiasm/cs/chapter_3_7.1727464700.txt.gz · Last modified: 2024/09/27 19:18 by pczekalski