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Components of Processor: Registers, ALU, Bus Control, Instruction Decoder

From our perspective, the processor is the electronic integrated circuit that controls other elements of the computer. Its main ability is to execute instructions. While we will go into details of the instruction set you will see that some of the instructions perform calculations or process data, but some of them do not. This suggests that the processor is composed of two main units. One of them is responsible for instruction execution while the second performs data processing. The first one is called the control unit or instruction processor, the second one is named the execution unit or data processor. We can see them in Fig 1.

Units of the processor
Figure 1: Units of the processor

Control unit

The function of the control unit, known also as the instruction processor is to fetch, decode and execute instructions. It also generates signals to the execution unit if the instruction being executed requires so. It is a synchronous and sequential unit. Synchronous means that it changes state synchronously with the clock signal. Sequential means that the next state depends on the states at the inputs and the current internal state. As inputs, we can consider not only physical signals from other units of the computer but also the code of the instruction. To ensure that the computer behaves the same every time it is powered on, the execution unit is set to the known state at the beginning of operation by RESET signal. Elements of the control unit are shown in Fig 2.

Elements of the control unit
Figure 2: Elements of the control unit

The control unit executes instructions in a few steps:

  • Generates the address of the instruction.
  • Fetches instruction code from memory.
  • Decodes instructions.
  • Generates signals to the execution unit or executes instructions internally.

In detail, the process looks as follows:

  1. The control unit takes the address of the instruction to be executed from a special register known as the Instruction Pointer or Program Counter and sends it to the memory via the address. It also generates signals on the control bus to synchronise memory with the processor.
  2. Memory takes the code of instruction from the provided address and sends it to the processor using a data bus.
  3. The processor stores the instruction code in the instruction register and based on the bit pattern interprets what to do next.
  4. If the instruction requires the execution unit operation, the control unit generates signals to control it. In cooperation with the execution unit, it can also read data from or write data to the memory.

The control unit works according to the clock signal generator cycles known as main clock cycles. With every clock cycle, some internal operations are performed. One such operation is reading or writing the memory which sometimes requires more than a single clock cycle. Single memory access is known as a machine cycle. As instruction execution sometimes requires more than one memory access and other actions the execution of the whole instruction is named instruction cycle. Summarising one instruction execution requires one instruction cycle, and several machine cycles, each composed of a few main clock cycles. Modern advanced processors are designed in such a way that they are able to execute a single instruction (sometimes even more than one) every single clock cycle. This requires a more complex design of a control unit, many execution units and other advanced techniques which makes it possible to process more than one instruction at a time.

The control unit also accepts input signals from peripherals enabling the interrupts and direct memory access mechanisms. For proper return from the interrupt subroutine, the control unit uses a special register called stack pointer. Interrupts and direct memory access mechanisms will be explained in detail in further chapters.

Although the stack pointer is not implemented in all modern processors, every processor has some mechanism for storing the returning address.

Fig 3.

Elements of the CISC execution unit
Figure 3: Elements of the CISC execution unit
en/multiasm/cs/chapter_3_4.1736001357.txt.gz · Last modified: 2025/01/04 14:35 by ktokarz
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