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--- en:multiasm:cs:chapter_3_4 [2025/01/04 11:26] – ktokarz
+++ en:multiasm:cs:chapter_3_4 [2025/12/02 11:05] (current) – [Execution unit] ktokarz
@@ Line 1: / Line 1: @@
-====== CISC, RISC ======
+======Components of Processor: Registers, ALU, Bus Control, Instruction Decoder ======
-It is not only the whole computer that can have a different architecture. This also touches processors. There are two main internal architectures of processors: CISC and RISC. CISC means Complex Instruction Set Computer while RISC stands for Reduced Instruction Set Computer. The naming difference can be a little confusing because it considers the instruction set to be complex or reduced. We can find CISC and RISC processors with similar number of instructions implemented. The difference is rather in the complexity of instructions not only the instruction set.
+From our perspective, the processor is the electronic integrated circuit that controls other elements of the computer. Its main ability is to execute instructions. While we will go into details of the instruction set, you will see that some instructions perform calculations or process data, while others do not. This suggests that the processor comprises two main units. One of them is responsible for instruction execution, while the second performs data processing. The first one is called the control unit or instruction processor. The second one is named the execution unit or data processor. We can see them in Fig {{ref>procblock}}.
-Complex instructions mean that the typical single instruction of a CISC processor makes more during its execution than typical RISC instruction. It also uses more sophisticated addressing. It means that if we want to make some algorithm we can use fewer CISC instructions in comparison to more RISC instructions. Of course, it comes with the price of a more sophisticated construction of CISC processor than RISC which influences the average execution time of a single instruction. As a result, the overall execution time can be similar, but in CISC more effort is done by the processor while in RISC more work is done by the compiler (or assembler programmer).
+<figure procblock>
+{{ :en:multiasm:cs:block_schematic_processor.png?600 |Units of the processor}}
+<caption>Units of the processor</caption>
+</figure>
-Additionally, there are differences in the general-purpose registers. In CISC the number of registers is smaller than in RISC. Additionally, they are specialised. It means that not all operations can be done with the use of any register. For example in some CISC processors arithmetic calculations can be done only with the use of a special register called accumulator, while addressing of table element or using a pointer can be done with the use of a special index (or base) register. In RISC almost all registers can be used for any purpose like the mentioned calculations or addressing. In CISC processors instructions have usually two arguments having the form of
+===== Control unit =====
-<code>
+The function of the control unit, also known as the instruction processor, is to fetch, decode and execute instructions. It also generates signals to the execution unit if the instruction being executed requires so. It is a synchronous and sequential unit. Synchronous means that it changes state synchronously with the clock signal. Sequential means that the next state depends on the states at the inputs and the current internal state. As inputs, we can consider not only physical signals from other units of the computer but also the code of the instruction. To ensure that the computer behaves the same every time it is powered on, the execution unit is set to the known state at the beginning of operation by the RESET signal.
-operation arg1, arg2    ; Example: arg1 = arg1 + arg2
+A typical control unit contains some essential elements:
-</code>
+  * Instruction register (IR).
-In such a situation //arg1// is one of a source and also a destination - place for the result. It destroys the original //arg1// value. In many RISC processors three argument instructions are present:
+  * Instruction decoder.
-<code>
+  * Program counter (PC)/instruction pointer (IP).
-operation arg1, arg2, arg3 ; Example: arg3 = arg1 + arg2
+  * Stack pointer (SP).
-</code>
+  * Bus interface unit.
-In such an approach two arguments are the source and the third one is the destination - original arguments are preserved and can be used for further calculations.
+  * Interrupt controller.
-The table summarises the difference between CISC and RISC processors.
+Elements of the control unit are shown in Fig {{ref>controlunit}}.
-^ Feature                      ^ CISC              ^ RISC               ^
+<figure controlunit>
-| Instructions                 | Complex           | Simple             |
+{{ :en:multiasm:cs:control_unit.png?600 |Elements of the control unit}}
-| Registers                    | Specialised       | Universal          |
+<caption>Elements of the control unit</caption>
-| Number of registers          | Smaller           | Larger             |
+</figure>
-| Calculations                 | With accumulator  | With any register  |
-| Addressing modes             | Complex           | Simple             |
+The control unit executes instructions in a few steps:
-| Non destroying instructions  | No                | Yes                |
+  * Generates the address of the instruction.
-| Examples of processors       | 8086, 8051        | AVR, ARM           |
+  * Fetches instruction code from memory.
+  * Decodes instructions.
+  * Generates signals to the execution unit or executes instructions internally.
+In detail, the process looks as follows:
+  - The control unit takes the address of the instruction to be executed from a special register known as the Instruction Pointer or Program Counter and sends it to the memory via the address bus. It also generates signals on the control bus to synchronise memory with the processor.
+  - Memory takes the code of instruction from the provided address and sends it to the processor using a data bus.
+  - The processor stores the instruction code in the instruction register and, based on the bit pattern, interprets what to do next.
+  - If the instruction requires the execution unit operation, the control unit generates signals to control it. In cooperation with the execution unit, it can also read data from or write data to the memory.
+The control unit works according to the clock signal generator cycles known as main clock cycles. With every clock cycle, some internal operations are performed. One such operation is reading or writing the memory, which sometimes requires more than a single clock cycle. Single memory access is known as a machine cycle. As instruction execution sometimes requires more than one memory access and other actions, the execution of the whole instruction is named an instruction cycle. Summarising, one instruction execution requires one instruction cycle and several machine cycles, each composed of a few main clock cycles. Modern advanced processors are designed in such a way that they are able to execute a single instruction (sometimes even more than one) every single clock cycle. This requires a more complex design of a control unit, many execution units and other advanced techniques, which makes it possible to process more than one instruction at a time.
+The control unit also accepts input signals from peripherals, enabling interrupts and direct memory access mechanisms. For proper return from the interrupt subroutine, the control unit uses a special register called the stack pointer. Interrupts and direct memory access mechanisms will be explained in detail in further chapters.
+<note>
+Although the stack pointer is not implemented in all modern processors, every processor has some mechanism for storing the returning address.
+</note>
+===== Execution unit =====
+An execution unit, also known as the data processor, executes instructions. Typically, it is composed of a few essential elements:
+  * Arithmetic logic unit (ALU).
+  * Accumulator and set of registers,
+  * Flags register,
+  * Temporal register.
+The arithmetic logic unit (ALU) is the element that performs logical and arithmetical calculations. It uses data coming from registers, the accumulator or from memory. Data coming from memory for arithmetic and logic instructions is stored in the temporal register. The result of calculations is stored back in the accumulator, another register or memory. In some legacy CISC processors, the only possible place for storing the result is the accumulator.
+Besides the result, ALU also returns some additional information about the calculations. It modifies the bits in the flag register, which comprises flags that are modified according to the results from arithmetic and logical operations. For example, if the result of the addition operation is too large to be stored in the resulting argument, the carry flag is set to indicate such a situation.
+Typically, the flags register includes:
+  * Carry flag, set in case a carry or borrow occurs.
+  * Sign flag, indicating whether the result is negative.
+  * Zero flag, set in case the result is zero.
+  * Auxiliary Carry flag used in BCD operations.
+  * Parity flag, which indicates whether the result has an even number of ones.
+The flags are used as conditions for decision-making instructions (like //if// statements in some high-level languages).
+The flags register can also implement some control flags to enable/disable processor functionalities. An example of such a flag can be the Interrupt Enable flag from the 8086 microprocessor.
+===== Registers =====
+Registers are memory elements which are placed logically and physically very close to the arithmetic logic unit. It makes them the fastest memory in the whole computer. They are sometimes called scratch registers, and the set of registers is called the register file.
+As we mentioned in the chapter about CISC and RISC processors, in CISC processors, registers are specialised, including the accumulator. A typical CISC execution unit is shown in Fig {{ref>CISCexeunit}}.
+<figure CISCexeunit>
+{{ :en:multiasm:cs:CISC_execution_unit.png?600 |Elements of the CISC execution unit}}
+<caption>Elements of the CISC execution unit</caption>
+</figure>
+A typical RISC execution unit does not have a specialised accumulator register. It implements the set of scratch registers as shown in Fig {{ref>RISCexeunit}}.
+<figure RISCexeunit>
+{{ :en:multiasm:cs:RISC_execution_unit.png?600 |Elements of the RISC execution unit}}
+<caption>Elements of the RISC execution unit</caption>
+</figure>

en/multiasm/cs/chapter_3_4.1735990005.txt.gz · Last modified: 2025/01/04 11:26 by ktokarz