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The classical architecture of computers uses a single address, and single data bus to connect the processor, memory and peripherals. This architecture is called von Neumann or Princeton, and we showed it in Fig. 1. Additionally in this architecture, the memory contains the code of programs and data the programs use. This suffers the drawback of the impossibility of accessing the instruction of the program and data to be processed at the same time, called the von Neumann bottleneck. The answer for this issue is the Harvard architecture, where program memory is separated from the data memory and they are connected to the processor with two pairs of address and data buses. Of course, the processor must support such type of architecture. The Harvard architecture we show in Fig. 2.