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| en:multiasm:cs:chapter_3_13 [2025/01/08 21:16] – ktokarz | en:multiasm:cs:chapter_3_13 [2025/12/12 09:47] (current) – ktokarz | ||
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| ====== DMA ====== | ====== DMA ====== | ||
| - | Direct memory access (DMA) is the mechanism for fast data transfer between peripherals and memory. In some implementations, | + | Direct memory access (DMA) is the mechanism for fast data transfer between peripherals and memory. In some implementations, |
| - | DMA controller is a specialised unit which can control the data transfer process. It implements several channels each containing the address register which is used to address the memory location and counter to specify how many cycles should be performed. | + | The DMA controller is a specialised unit which can control the data transfer process. It implements several channels, each containing the address register, which is used to address the memory location and a counter to specify how many cycles should be performed. |
| <figure DMAinactive> | <figure DMAinactive> | ||
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| </ | </ | ||
| - | The process of data transfer is done in some steps, Let us consider the situation when a peripheral has some data to be transferred. | + | The process of data transfer is done in some steps. Let us consider the situation when a peripheral has some data to be transferred. |
| * peripheral signals the request to transfer data (DREQ). | * peripheral signals the request to transfer data (DREQ). | ||
| * DMA controller forwards the request to the processor (HOLD). | * DMA controller forwards the request to the processor (HOLD). | ||
| - | * The processor accepts the DMA cycle (HLDA) and switches off from the busses. | + | * The processor accepts the DMA cycle (HLDA) and switches off from the buses. |
| * DMA controller generates the address on the address bus and sends the acknowledge signal to the peripheral (DACK). | * DMA controller generates the address on the address bus and sends the acknowledge signal to the peripheral (DACK). | ||
| - | * Peripheral sends the data by the data bus. | + | * Peripheral sends the data on the data bus. |
| * DMA generates a write signal to store data in the memory. | * DMA generates a write signal to store data in the memory. | ||
| - | * DMA controller updates address register and the counter. | + | * DMA controller updates |
| - | * If the counter reaches zero data transfer stops. | + | * If the counter reaches zero, data transfer stops. |
| - | Everything is done without any action of the processor, no program is fetched and executed. Because everything is done by hardware the transfer can be done in one memory access cycle so much faster than by the processor. Data transfer by processor is significantly slower because requires at least four instructions of program execution and two data transfers: one from the peripheral and another to the memory for one cycle. The system with an active DMA controller is presented in Fig.{{ref> | + | Everything is done without any action of the processor. No program is fetched and executed. Because everything is done by hardware, the transfer can be done in one memory access cycle, so much faster than by the processor. Data transfer by the processor is significantly slower because |
| <figure DMAactive> | <figure DMAactive> | ||
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| * Transparent - DMA works when the CPU is executing instructions | * Transparent - DMA works when the CPU is executing instructions | ||
| + | DMA controllers are implemented in personal computers, but also in advanced microcontrollers and systems on a chip, to support data transfers between internal memory and internal peripherals. | ||
