Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | |||
| en:multiasm:cs:chapter_3_13 [2025/01/08 21:13] – ktokarz | en:multiasm:cs:chapter_3_13 [2025/01/08 21:16] (current) – ktokarz | ||
|---|---|---|---|
| Line 19: | Line 19: | ||
| * If the counter reaches zero data transfer stops. | * If the counter reaches zero data transfer stops. | ||
| - | Everything is done without any action of the processor, no program is fetched and executed. Because everything is done by hardware the transfer can be done in one memory access cycle. Data transfer by processor requires program execution and two data transfers: one from the peripheral and another to the memory. The system with an active DMA controller is presented in Fig.{{ref> | + | Everything is done without any action of the processor, no program is fetched and executed. Because everything is done by hardware the transfer can be done in one memory access cycle so much faster than by the processor. Data transfer by processor |
| <figure DMAactive> | <figure DMAactive> | ||
