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| en:multiasm:cs:chapter_3_13 [2025/01/08 21:11] – ktokarz | en:multiasm:cs:chapter_3_13 [2025/01/08 21:16] (current) – ktokarz | ||
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| * peripheral signals the request to transfer data (DREQ). | * peripheral signals the request to transfer data (DREQ). | ||
| * DMA controller forwards the request to the processor (HOLD). | * DMA controller forwards the request to the processor (HOLD). | ||
| - | * Processor | + | * The processor |
| * DMA controller generates the address on the address bus and sends the acknowledge signal to the peripheral (DACK). | * DMA controller generates the address on the address bus and sends the acknowledge signal to the peripheral (DACK). | ||
| * Peripheral sends the data by the data bus. | * Peripheral sends the data by the data bus. | ||
| Line 19: | Line 19: | ||
| * If the counter reaches zero data transfer stops. | * If the counter reaches zero data transfer stops. | ||
| - | Everything is done without any action of the processor, no program is fetched and executed. Because everything is done by hardware the transfer can be done in one memory access cycle. Data transfer by processor requires program execution and two data transfers: one from the peripheral and another to the memory. The system with an active DMA controller is presented in Fig.{{ref> | + | Everything is done without any action of the processor, no program is fetched and executed. Because everything is done by hardware the transfer can be done in one memory access cycle so much faster than by the processor. Data transfer by processor |
| <figure DMAactive> | <figure DMAactive> | ||
