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--- en:multiasm:cs:chapter_3_13 [2025/12/12 09:39] – ktokarz
+++ en:multiasm:cs:chapter_3_13 [2025/12/12 09:47] (current) – ktokarz
@@ Line 2: / Line 2: @@
 Direct memory access (DMA) is the mechanism for fast data transfer between peripherals and memory. In some implementations, it is also possible to transfer data between two peripherals or from memory to memory. DMA operates without the activity of the processor. No software is executed during the DMA transfer. It must be supported by a processor and peripheral hardware, and there must be a DMA controller present in the system. The controller plays the main role in transferring the data.
-The DMA controller is a specialised unit which can control the data transfer process. It implements several channels, each containing the address register, which is used to address the memory location and a counter to specify how many cycles should be performed. The address register and counter must be programmed by the processor. It is usually done in the system startup procedure. The system with an inactive DMA controller is presented in Fig.{{ref>DMAinactive}}.
+The DMA controller is a specialised unit which can control the data transfer process. It implements several channels, each containing the address register, which is used to address the memory location and a counter to specify how many cycles should be performed. The address and counter registers have corresponding temporal address and counter registers updated after every single transfer. The address register and counter must be programmed by the processor. It is usually done in the system startup procedure. The system with an inactive DMA controller is presented in Fig.{{ref>DMAinactive}}.
 <figure DMAinactive>

en/multiasm/cs/chapter_3_13.txt · Last modified: 2025/12/12 09:47 by ktokarz