Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| en:multiasm:cs:chapter_3_12 [2025/01/08 20:40] – [Recognizing interrupt source] ktokarz | en:multiasm:cs:chapter_3_12 [2025/01/08 20:42] (current) – [Recognizing interrupt source] ktokarz | ||
|---|---|---|---|
| Line 2: | Line 2: | ||
| An interrupt is a request to the processor to temporarily suspend the currently executing code in order to handle the event that caused the interrupt. If the request is accepted by the processor, it saves its state and performs a function named an interrupt handler or interrupt service routine (ISR). Interrupts are usually signalled by peripheral devices in a situation while they have some data to process. Often, peripheral devices do not send an interrupt signal directly to the processor, but there is an interrupt controller in the system that collects requests from various peripheral devices. The interrupt controller prioritizes the peripherals to ensure that the more important requests are handled first. | An interrupt is a request to the processor to temporarily suspend the currently executing code in order to handle the event that caused the interrupt. If the request is accepted by the processor, it saves its state and performs a function named an interrupt handler or interrupt service routine (ISR). Interrupts are usually signalled by peripheral devices in a situation while they have some data to process. Often, peripheral devices do not send an interrupt signal directly to the processor, but there is an interrupt controller in the system that collects requests from various peripheral devices. The interrupt controller prioritizes the peripherals to ensure that the more important requests are handled first. | ||
| + | |||
| + | From a hardware perspective, | ||
| + | * Level triggered - stable low or high level signals the interrupt. While the interrupt handler is finished and the interrupt signal is still active the interrupt is signalled again. | ||
| + | * Edge triggered - interrupt is signalled only while there is a change on interrupt input. The falling or rising edge of the interrupt signal. | ||
| The interrupt signal comes asynchronously which means that it can come during execution of the instruction. Usually, the processor finishes this instruction and then calls the interrupt handler. To be able to handle interrupts the processor must implement the mechanism of storing the address of the next instruction to be executed in the interrupted code. Some implementations use the stack while some use a special register to store the returning address. The latter approach requires software support if interrupts can be nested (if the interrupt can be accepted while already in another ISR). | The interrupt signal comes asynchronously which means that it can come during execution of the instruction. Usually, the processor finishes this instruction and then calls the interrupt handler. To be able to handle interrupts the processor must implement the mechanism of storing the address of the next instruction to be executed in the interrupted code. Some implementations use the stack while some use a special register to store the returning address. The latter approach requires software support if interrupts can be nested (if the interrupt can be accepted while already in another ISR). | ||
| Line 14: | Line 18: | ||
| </ | </ | ||
| - | ===== Recognizing | + | ===== Recognising |
| To properly handle the interrupts the processor must recognise the source of the interrupt. Different code should be executed when the interrupt is signalled by a network controller, different if the source of the interrupt is a timer. The information on the interrupt source is provided to the processor by the interrupt controller or directly by the peripheral. | To properly handle the interrupts the processor must recognise the source of the interrupt. Different code should be executed when the interrupt is signalled by a network controller, different if the source of the interrupt is a timer. The information on the interrupt source is provided to the processor by the interrupt controller or directly by the peripheral. | ||
| We can distinguish three main methods of calling proper ISR for incoming interrupts. | We can distinguish three main methods of calling proper ISR for incoming interrupts. | ||
| Line 30: | Line 34: | ||
| In microprocessors, | In microprocessors, | ||
| - | ===== Hardware signals on interrupt input ===== | + | |
| - | From a hardware perspective, | + | |
| - | * Level triggered - stable low or high level signals the interrupt. While the interrupt handler is finished and the interrupt signal is still active the interrupt is signalled again. | + | |
| - | * Edge triggered - interrupt is signalled only while there is a change on interrupt input. The falling or rising edge of the interrupt signal. | + | |
| ===== Software and internal interrupts ===== | ===== Software and internal interrupts ===== | ||
