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--- en:multiasm:cs:chapter_3_12 [2025/01/08 19:30] – ktokarz
+++ en:multiasm:cs:chapter_3_12 [2025/01/08 20:42] (current) – [Recognizing interrupt source] ktokarz
@@ Line 2: / Line 2: @@
 An interrupt is a request to the processor to temporarily suspend the currently executing code in order to handle the event that caused the interrupt. If the request is accepted by the processor, it saves its state and performs a function named an interrupt handler or interrupt service routine (ISR). Interrupts are usually signalled by peripheral devices in a situation while they have some data to process. Often, peripheral devices do not send an interrupt signal directly to the processor, but there is an interrupt controller in the system that collects requests from various peripheral devices. The interrupt controller prioritizes the peripherals to ensure that the more important requests are handled first.
+From a hardware perspective, an interrupt can be signalled with the signal state or change.
+  * Level triggered - stable low or high level signals the interrupt. While the interrupt handler is finished and the interrupt signal is still active the interrupt is signalled again.
+  * Edge triggered - interrupt is signalled only while there is a change on interrupt input. The falling or rising edge of the interrupt signal.
 The interrupt signal comes asynchronously which means that it can come during execution of the instruction. Usually, the processor finishes this instruction and then calls the interrupt handler. To be able to handle interrupts the processor must implement the mechanism of storing the address of the next instruction to be executed in the interrupted code. Some implementations use the stack while some use a special register to store the returning address. The latter approach requires software support if interrupts can be nested (if the interrupt can be accepted while already in another ISR).
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-===== Recognizing interrupt source =====
+===== Recognising interrupt source =====
-Fixed – microcontrollers.
+To properly handle the interrupts the processor must recognise the source of the interrupt. Different code should be executed when the interrupt is signalled by a network controller, different if the source of the interrupt is a timer. The information on the interrupt source is provided to the processor by the interrupt controller or directly by the peripheral.
-every interrupt handler has its own fixed starting address.
+We can distinguish three main methods of calling proper ISR for incoming interrupts.
-Vectored – microprocessors.
+  * Fixed – microcontrollers. Every interrupt handler has its own fixed starting address.
-one interrupt pin, peripheral sends address of handler through data bus.
+  * Vectored – microprocessors. There is one interrupt pin, the peripheral sends the address of the handler through the data bus.
-Indexed – microprocessors.
+  * Indexed – microprocessors. The peripheral sends an interrupt number. It is used as the index in the table of handlers' addresses.
-peripheral sends number of the interrupt – index in the table of handlers' addresses.
+===== Maskable and non-maskable interrupts =====
+Interrupts can be enabled or disabled. Disabling interrupts is often used for time-critical code to ensure the shortest possible execution time. Interrupts which can be disabled are named maskable interrupts. They can be disabled with the corresponding flag in the control register. In microcontrollers, there are separate bits for different interrupts.
+If an interrupt can not be disabled is named non-maskable interrupt. Such interrupts are implemented for critical situations:
+  * memory failure
+  * power down
+  * critical hardware errors
+In microprocessors, there exists separate non-maskable interrupt input – NMI.
-Maskable interrupt – can be disabled with the special flag.
-Interrupts usually can be masked.
-In microcotrollers separate bits for different interrupts.
-Disabling interrupts for time critical code.
-Non maskable interrupt – cannot be disabled.
-Separate interrupt input – NMI.
-Reserved usually for critical situation:
-Memory failure
-Power down
-Level triggered.
+===== Software and internal interrupts =====
-While interrupt handler is finished and interrupt signal is still active interrupt is signalled again.
+In some processors, it is possible to signal the interrupt by executing special instructions. They are named software interrupts and can be used to test interrupt handlers. In some operating systems (DOS, Linux) software interrupts are used to implement the mechanism of calling system functions.
-Low level on interrput input.
-High level on interrupt input.
-Edge triggered.
-Interrupt is signalled only while there is a change on interrupt input.
-Falling edge of interrupt signal.
-Rising edge of interrupt signal.
-Software interrupts
+Another group of interrupts signalled by the processor itself are internal interrupts. They aren't signalled with special instruction but rather in some specific situations during normal program execution.
-Internal interrupts
+  * Exceptions – generated by abnormal behaviour in some instructions (e.g. dividing by 0).
-Exception – generated by abnormal behavior in some instructions (dividing by 0).
+  * Trap – intentionally initiated by programmer transfer control to handler routine (e.g. for debugging).
-Trap – intentionally initiated by programmer transfer control to handler routine (debugging).
+  * Fault – generated while detecting some errors in the program (memory protection, invalid code of operation).
-Fault – generated while detecting some errors in the program (memory protection, invalid code of operation).

en/multiasm/cs/chapter_3_12.1736364617.txt.gz · Last modified: 2025/01/08 19:30 by ktokarz