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--- en:multiasm:cs:chapter_3_12 [2025/12/12 07:22] – ktokarz
+++ en:multiasm:cs:chapter_3_12 [2025/12/12 09:17] (current) – ktokarz
@@ Line 5: / Line 5: @@
 From a hardware perspective, an interrupt can be signalled with the signal state or change.
   * Level triggered - stable low or high level signals the interrupt. While the interrupt handler is finished and the interrupt signal is still active, the interrupt is signalled again.
-  * Edge-triggered - interrupt is signalled only while there is a change in the interrupt input. The falling or rising edge of the interrupt signal.
+  * Edge-triggered - the interrupt is signalled only while there is a change in the interrupt input. The falling or rising edge of the interrupt signal.
-The interrupt signal comes asynchronously which means that it can come during execution of the instruction. Usually, the processor finishes this instruction and then calls the interrupt handler. To be able to handle interrupts the processor must implement the mechanism of storing the address of the next instruction to be executed in the interrupted code. Some implementations use the stack while some use a special register to store the returning address. The latter approach requires software support if interrupts can be nested (if the interrupt can be accepted while already in another ISR).
+The interrupt signal comes asynchronously, which means that it can come during the execution of the instruction. Usually, the processor finishes this instruction and then calls the interrupt handler. To be able to handle interrupts, the processor must implement the mechanism of storing the address of the next instruction to be executed in the interrupted code. Some implementations use the stack, while others use a special register to store the return address. The latter approach requires software support if interrupts can be nested (if the interrupt can be accepted while already in another ISR).
-After finishing the interrupt subroutine processor uses the returning address to return back program control to the interrupted code.
+After finishing the interrupt subroutine processor uses the returning address to return program control back to the interrupted code.
-The Fig. {{ref>interrupt}} shows how interrupt works with stack use. The processor executes the program. When an interrupt comes it saves the return address on the stack. Next jumps to the interrupt handler. With //return// instruction processor returns to the program taking the address of an instruction to execute from the stack.
+The Fig. {{ref>interrupt}} shows how interrupt works with stack use. The processor executes the program. When an interrupt comes, it saves the return address on the stack. Next jumps to the interrupt handler. With //return// instruction processor returns to the program, taking the address of an instruction to execute from the stack.
 <figure interrupt>
@@ Line 29: / Line 29: @@
 Interrupts can be enabled or disabled. Disabling interrupts is often used for time-critical code to ensure the shortest possible execution time. Interrupts which can be disabled are named maskable interrupts. They can be disabled with the corresponding flag in the control register. In microcontrollers, there are separate bits for different interrupts.
-If an interrupt can not be disabled is named non-maskable interrupt. Such interrupts are implemented for critical situations:
+If an interrupt can not be disabled is named a non-maskable interrupt. Such interrupts are implemented for critical situations:
   * memory failure
   * power down
   * critical hardware errors
-In microprocessors, there exists separate non-maskable interrupt input – NMI.
+In microprocessors, there exists a separate non-maskable interrupt input – NMI.
 ===== Software and internal interrupts =====
-In some processors, it is possible to signal the interrupt by executing special instructions. They are named software interrupts and can be used to test interrupt handlers. In some operating systems (DOS, Linux) software interrupts are used to implement the mechanism of calling system functions.
+In some processors, it is possible to signal the interrupt by executing special instructions. They are named software interrupts and can be used to test interrupt handlers. In some operating systems (DOS, Linux), software interrupts are used to implement the mechanism of calling system functions.
-Another group of interrupts signalled by the processor itself are internal interrupts. They aren't signalled with special instruction but rather in some specific situations during normal program execution.
-  * Exceptions – generated by abnormal behaviour in some instructions (e.g. dividing by 0).
-  * Trap – intentionally initiated by programmer transfer control to handler routine (e.g. for debugging).
-  * Fault – generated while detecting some errors in the program (memory protection, invalid code of operation).
+Another group of interrupts signalled by the processor itself are internal interrupts. They aren't signalled with special instructions but rather in some specific situations during normal program execution. They are called exceptions and can be divided into three groups.
+  * Faults – generated by abnormal behaviour in some instructions (e.g. dividing by 0).
+  * Traps – intentionally initiated by the programmer to transfer control to a handler routine (e.g. for debugging).
+  * Aborts – generated while detecting some serious errors in the program of computer behaviour (e.g. memory error).
+Faults are not real errors. They are often used by the operating system to perform normal operations like handling the paging mechanism.

en/multiasm/cs/chapter_3_12.txt · Last modified: 2025/12/12 09:17 by ktokarz