====== CISC, RISC ======

It is not only the whole computer that can have a different architecture. This also touches processors. There are two main internal processor architectures: CISC and RISC. CISC stands for Complex Instruction Set Computer, while RISC stands for Reduced Instruction Set Computer. The naming difference can be a little confusing because it treats the instruction set as complex or reduced. We can find CISC and RISC processors with a similar number of instructions implemented. The difference is rather in the complexity of instructions, not just the instruction set.

Complex instructions mean that a typical single CISC processor instruction performs more operations during its execution than a typical RISC instruction. The CISC processors also implement more sophisticated addressing modes. This means that if we want to implement an algorithm, we can use fewer CISC instructions compared to more RISC instructions. Of course, it comes with the price of a more sophisticated construction of a CISC processor than RISC. The complexity of a circuit influences the average execution time of a single instruction. As a result, the CISC processor does more work during program execution, while in RISC, the compiler (or assembler programmer) does more work during the implementation phase. 

The most visible distinguishing features between RISC and CISC architectures to a programmer lie in the general-purpose registers and instruction operands. Typically, in CISC, the number of registers is smaller than in RISC. Additionally, they are specialised. It means that not all operations can be performed using any register. For example, in some CISC processors, arithmetic calculations can be done only with the use of a special register called the accumulator, while addressing of a table element or using a pointer can be done with the use of a special index (or base) register. In RISC, almost all registers can be used for any purpose, like the mentioned calculations or addressing. In CISC processors, instructions usually have two arguments in the form of:
<code>
operation arg1, arg2    ; Example: arg1 = arg1 + arg2
</code>
In such a situation, //arg1// is one of the sources and also a destination - the place for the result. It destroys the original //arg1// value. In many RISC processors, three-argument instructions are present:
<code>
operation arg1, arg2, arg3 ; Example: arg3 = arg1 + arg2
</code>
In such an approach, two arguments are the source, and the third one is the destination - original arguments are preserved and can be used for further calculations.
The table {{ref>ciscrisc}} summarises the difference between CISC and RISC processors. 

<table ciscrisc>
<caption>CISC and RISC features</caption>
^ Feature                      ^ CISC              ^ RISC               ^
| Instructions                 | Complex           | Simple             |
| Registers                    | Specialised       | Universal          |
| Number of registers          | Smaller           | Larger             |
| Calculations                 | With accumulator  | With any register  |
| Addressing modes             | Complex           | Simple             |
| Non destroying instructions  | No                | Yes                |
| Examples of processors       | 8086, 8051        | AVR, ARM           |
</table>

All these features make the RISC architecture more flexible, allowing the programmer or compiler to create code without unnecessary data transfer. The execution units of RISC processors can be simpler in construction, enabling higher operating frequencies and faster program execution. What is interesting is that the modern versions of popular CISC machines, such as Intel and AMD processors used in personal computers, internally translate CISC instructions into RISC microoperations, which are executed by execution units.
A simple instruction can be converted directly into a single microoperation. Complex instructions are often implemented as sequences of microoperations called microcodes.